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Cost‐effective resilience in integrated circuits from the architectural to technology level



Datum: 28.02.2017
Uhrzeit: 16.00 Uhr c.t.

Ort: Cartesium Rotunde



[ Dr. Maksim Jenihhin Prof. Dr. Jaan Raik ]

In this talk Prof. Jaan Raik and Dr. Maksim Jenihhin will give an overview of some research activities run at Tallinn UT. In particular, fault resilience vs fault tolerance will be addressed for many‐core processors on the architectural level. Automated design error localization that supports improvement of resilience and localization of problems in a circuit will be discussed for the Register Transfer Level (RTL). Finally, aging aspects mainly driven by Negative‐bias Temperature Instability (NBTI) effects and their mitigation by a rejuvenation technique will be presented.

Biographies

Jaan Raik is a professor of digital systems verification at the Department of Computer Engineering of Tallinn University of Technology and the leader of the Dependable Computing Systems Design (DCSD) research group that obtained the highest grades in the 5/2015 International Evaluation Report of ICT Research in Estonia. He received M.Sc. and Ph.D. degrees in Computer Engineering from Tallinn University of Technology in 1997 and in 2001, respectively. He co‐authored more than 200 scientific publications. Among other awards he received the Order of the White Star 4th class medal by the President of Estonia (2016). He currently coordinates the Horizon 2020 RIA IMMORTAL and the Horizon 2020 Twinning project TUTORIAL.

Maksim Jenihhin is a senior research fellow at the Department of Computer Engineering, Tallinn University of Technology PhD degree in 2008. His primary research interests include HW verification and debug, reliability assessment and enhancement, manufacturing test as well as EDA methodologies. Maksim is a co‐founder of the Biannual European ‐ Latin American Summer School BELAS and coordinates a new European Training Network H2020 MSCA ITN RESCUE.





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