Scope of the workshop and target audience

Understanding a hardware design is tough. When entering a large team as a new member, when extending a legacy design, or when documenting a new design, a lack in understanding the details of a design is a major obstacle for productivity. In software engineering topics like software maintenance, software understanding, reverse engineering are well established in the research community and partially tackled by tools. In the hardware area the re-use of IP-blocks, the growing size of designs and design teams leads to similar problems. Understanding of hardware requires deep insight into concurrently operating units, optimizations to reduce the required area, and specially tailored functional units for a particular use.

The workshop is of interest to practitioners working in circuit design and to researchers interested in design automation.

The aim of the 2nd Workshop on Design Automation for Understanding Hardware Designs (DUHDe) is to consolidate the community for these topics in electronic design automation. The workshop is not limited to the following topics in design understanding but includes:


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Proceedings and
Invited Talks

  • Design descriptions from the ESL down to RTL
  • Extraction of high-level properties
  • Localization of code implementing specialized functionality
  • Hardware design evolution : feature integration, feature interactions
  • Innovative GUIs for design
  • Managing documentation of hardware designs
  • Analysis of interaction between hardware and software
  • Formal methods for design understanding
  • Scalable approaches to design understanding

Proceedings

The proceedings of DUHDe are only available for participants of the workshop.

Call for Papers and Submission Instructions


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Call for Papers

Prospective authors are requested to submit extended abstracts of 2 pages or full papers of 6 pages in IEEE conference style. Authors of accepted contributions are required to present their work at the workshop. Informal proceedings will be distributed electronically to the participants of the workshop. The authors retain the copyright of their work and are free to submit extended versions to a conference or journal. Alternatively posters may be submitted that will not be contained in the informal proceedings.

Contributions have to be submitted through Easychair:
https://easychair.org/conferences/?conf=duhde2015.


Deadline for extended abstracts or full papers:November 7, 2014
Extended deadline for extended abstracts or full papers:November 14, 2014
Notification of acceptance:December 1, 2014
Deadline for poster submissions:January 16, 2015
Notification for posters:January 25, 2015
Camera ready papers and posters:February 1, 2015

Registration

Please register through the DATE registration system for Workshop W04: https://react-profile.org/DATE2015/Registration/.

One author per paper must be registered by February 10, 2015.

Early registration ends February 10, 2015.

Event format

The workshop is organized as a Friday workshop associated to DATE 2015.

The topic of design understanding is relatively new as a research topic in hardware. The goal of the workshop is to solicit presentations that resemble early ideas or summarize existing work. The workshop will have the following elements:

  • Invited talk from industry on current issues
    • Eli Arbel, IBM Research, Haifa, Israel
  • Invited talks from academia on recent research results
    • Shobha Vasudevan, University of Illinois at Urbana-Champaign, USA
    • Matthieu Moy, Verimag, Grenoble, France
  • Long presentations: 25 minutes (18 min. presentation, 7 min. discussion)
  • Poster presentations
  • Panel discussion: Design Understanding - At What Abstraction Level is the Pain Most Intense?

Program

8:30 - 8:40Opening session
Chairs: Görschwin Fey, Emmanuelle Encrenaz-Tiphéne
8:40 - 9:20Invited talk 1
Practical applications of hardware design understanding using formal methods
Eli Arbel
IBM Research, Haifa, Israel
Technical session 1
9:20 - 9:45 SystemC-Based Loose Models: RTL Abstraction for Design Understanding
Syed Saif Abrar, Maksim Jenihhin and Jaan Raik
TU Tallinn
9:45 - 10:10 Ecore Model Generation from SystemC/C++ Implementations
Jannis Stoppe and Rolf Drechsler
University of Bremen
10:10 - 10:35 Towards analysing feature locations through testing traces with BUT4Reuse
Jabier Martinez1, Jan Malburg2, Tewfik Ziadi1 and Goerschwin Fey2,3
1Université Pierre et Marie Curie; 2University of Bremen; 3German Aerospace Center
10:35 - 11:00Coffee break
11:00 - 11:50Invited talk 2
Assertion Mining
Shobha Vasudevan
University of Illinois at Urbana-Champaign, USA
11:50 - 12:00 Poster teasers
12:00 - 13:00Lunch
Technical session 2
13:00 - 13:25Learning Grammars for Assertion Creation from Natural Language
Christopher Harris and Ian Harris
University of California Irvine
13:25 - 13:50 A Binding Method for Hierarchical Testability Using Results of Test Environment Generation
Jun Nishimaki1, Toshinori Hosokawa1 and Hideo Fujiwara2
1Nihon University; 2Osaka Gakuin University
13:50 - 14:40Invited Talk 3
Parallelization of SystemC-TLM simulations, and modelling of time and power consumption
Matthieu Moy
Verimag, Grenoble, France
14:40 - 15:30 Poster session and coffee break
Is there a chance that computers understand analog design?
Ramy Iskander, Farakh Javid and Marie-Minerve Louerat
Université Pierre et Marie Curie
Understanding the Heterogeneous Hardware: Do not forget the interconnection!
Liliana Andrade, Cédric Ben Aoun, Benoît Vernay, Torsten Maehne, Francois Pecheux and Marie-Minerve Louerat
Université Pierre et Marie Curie
AMS System-level exploration and verification using UVM in SystemC and SystemC AMS
Yao Li1, Zhi Wang1, Francois Pecheux1, Marie-Minerve Louerat1, Martin Barnasconi2, Thilo Voertler3 and Karsten Einwich3
1Université Pierre et Marie Curie ; 2NXP Semiconductors, Eindhoven; 3Fraunhofer IIS/EAS, Dresden
Debugging Hardware Designs Using Dynamic Dependency Graphs
Jan Malburg1, Alexander Finder2 and Goerschwin Fey1,3
1University of Bremen; 2Aventon GmbH; 3German Aerospace Center
Technical session 3
15:30 - 15:55 A simulator to understand the effects of fault injection attacks on a microcontroller
Nicolas Moro, Karine Heydemann, Bruno Robisson and Emmanuelle Encrenaz
Université Pierre et Marie Curie
15:55 - 16:40Panel
Design Understanding - At What Abstraction Level is the Pain Most Intense?

Moderator: Ian G. Harris, University of California Irvine

Lyes Benalycherif, ST Microelectronics
Dominique Borrione, TIMA
Franco Fummi, Università degli Studi di Verona
Jaan Raik, TU Tallinn