» Overcoming Limitations of the SystemC Data Introspection
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Author:
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Christian Genz, Rolf Drechsler |
| Conference: |
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Design Automation and Test in Europe (DATE)
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Reference:
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| Nice, 2009
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Hyperlink:
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| [Link to the Conference]
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» Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
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Author:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE)
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Reference:
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| Nice, 2009
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| [Link to the Conference]
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» Debugging of Toffoli Networks
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Author:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
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| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| Nice, 2009
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Hyperlink:
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| [Link to the Conference]
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» Increasing the Accuracy of SAT-based Debugging
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Author:
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Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| Nice, 2009
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Hyperlink:
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| [Link to the Conference]
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» Reversible Logic Synthesis with Output Permutation
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Author:
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Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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22nd International Conference on VLSI Design |
Reference:
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| New Delhi, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Formaler Nachweis der Fehlertoleranz von Schaltkreisen
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Author:
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Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Conference: |
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GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008) |
Reference:
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| pp. 75-82, Ingolstadt, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Verification of PLC Programs using Formal Proof Techniques
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Author:
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Andre Sülflow, Rolf Drechsler |
| Conference: |
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Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008) |
Reference:
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| Budapest, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Efficient Formal Verification of Track Vacancy Detection Sections
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Author:
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Sebastian Kinder und Rolf Drechsler |
| Conference: |
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Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
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Reference:
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| Budapest, 2008
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Hyperlink:
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| [Link to the Conference]
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» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
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Author:
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Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler |
| Conference: |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| Parma, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Contradiction Analysis for Constraint-based Random Simulation
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Author:
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Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| pp. 130-135, Stuttgart, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
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Author:
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Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Conference: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Reference:
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| pp. 411-416, Montpellier, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
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Author:
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Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
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| pp. 220-225, Dallas, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
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| pp. 214-219, Dallas, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
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| pp. 94-99, Dallas, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Using Unsatisfiable Cores to Debug Multiple Design Errors
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Author:
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Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Conference: |
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IEEE Great Lakes Symposium on VLSI (GLSVLSI'08) |
Reference:
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| Orlando, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs
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Author:
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Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner |
| Conference: |
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IEEE International Symposium on Circuits and Systems (ISCAS'08) |
Reference:
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| Seattle, 2008
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Hyperlink:
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| [Link to the Conference]
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» A Basis for Formal Robustness Checking
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Author:
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Görschwin Fey, Rolf Drechsler
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| Conference: |
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International Symposium on Quality of Electronic Design (ISQED) |
Reference:
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| San Jose, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Adaptive Branch and Bound using SAT to Estimate False Crosstalk
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Author:
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Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
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| Conference: |
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International Symposium on Quality of Electronic Design (ISQED) |
Reference:
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| San Jose, 2008
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Hyperlink:
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| [Link to the Conference]
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» Automatic Generation of Complex Properties for Hardware Designs
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Author:
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Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke |
| Conference: |
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Design, Automation, and Test in Europe (DATE) |
Reference:
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| Munich, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
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Author:
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Sujan Pandey, Rolf Drechsler |
| Conference: |
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Design, Automation, and Test in Europe (DATE) |
Reference:
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| Munich, 2008
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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