» Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
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Author:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
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9th International Workshop on Microprocessor Test and Verification (MTV) |
Reference:
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| Austin, Texas, 2008
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Hyperlink:
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| [Link to the Workshop]
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» Computing Bounds for Fault Tolerance using Formal Techniques
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Author:
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Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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IEEE Workshop on Design for Reliability and Variability (DRV) |
Reference:
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| Santa Clara, USA, 2008
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» Experimental Studies on SMT-based Debugging
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Author:
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Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08) |
Reference:
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| Japan, 2008
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» Reversible Logic Synthesis with Output Permutation
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Author:
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Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Workshop: |
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International Workshop on Boolean Problems |
Reference:
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| Freiberg, 2008
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Hyperlink:
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| [Link to the Workshop]
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» Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs
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Author:
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Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
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Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS) |
Reference:
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| Dresden, 2008
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Hyperlink:
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| [Link to the Workshop]
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» Contradiction Analysis for Constraint-based Random Simulation
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Author:
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Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Workshop: |
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Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
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Reference:
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| pp. 25-30, Dresden, 2008
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Hyperlink:
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| [Link to the Workshop]
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» Targeting Leakage Constraints during ATPG
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Author:
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Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
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| Workshop: |
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IEEE International Workshop on Silicon Debug and Diagnosis |
Reference:
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| San Diego, 2008
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» Synthesis for Detection of Transient Faults
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Author:
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Görschwin Fey, Rolf Drechsler
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| Workshop: |
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IEICE Workshop on Dependable Computing |
Reference:
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| IEICE Technical Report, Vol. 107, No. 558, pages 161-166, 2008
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» Formale Modellextraktion von SystemC Entwürfen
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Author:
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Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
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| Workshop: |
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edaWorkshop |
Reference:
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| Hannover 2008
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» Ad-Hoc Translations to Close Verilog Semantics Gap
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Author:
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Christian Haufe, Frank Rogin |
| Workshop: |
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11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems |
Reference:
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| Bratislava, 2008
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Hyperlink:
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| [Link to the Workshop]
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» Incremental SAT Instance Generation for SAT-based ATPG
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Author:
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Daniel Tille, Rolf Drechsler |
| Workshop: |
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11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems |
Reference:
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| Bratislava, 2008
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
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Author:
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Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| pp. 169-178, Freiburg, 2008
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Hyperlink:
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| [Link to the Workshop]
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» Debugging Design Errors by Using Unsatisfiable Cores
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Author:
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Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Workshop: |
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11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| Freiburg, 2008
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» False Noise Analysis Using Branch & Bound and SAT
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Author:
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Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler |
| Workshop: |
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ACM/IEEE International Workshop on Timing
Issues in the Specification and Synthesis of Digital Systems
(TAU 2008) |
Reference:
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| Monterey, 2008
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Hyperlink:
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| [Link to the Workshop]
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» Improved Circuit-to-CNF Transformation for SAT-based ATPG
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Author:
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Daniel Tille, René Krenz-Bååth, Jürgen Schlöffel, Rolf Drechsler |
| Workshop: |
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20. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
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Reference:
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| Wien, 2008
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
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Author:
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Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler |
| Workshop: |
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IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) |
Reference:
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| pp. 31-36, Beijing, P.R.China, 2007
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» Formal Robustness Checking
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Author:
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Görschwin Fey, Rolf Drechsler |
| Workshop: |
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Workshop on Constraints in Formal Verification, 2007 |
Reference:
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| Bremen, 2007
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PDF:
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| [click here]
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Hyperlink:
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| [Link to the Workshop]
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» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
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Author:
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Rolf Drechsler, Görschwin Fey, Jürgen Schlöffel |
| Workshop: |
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edaWorkshop 2007 |
Reference:
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| Hannover, 2007
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Hyperlink:
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| [Link to the Workshop]
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» On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-Micron Interconnects.
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Author:
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Tudor Murgan, Petru Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner |
| Workshop: |
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In Intl. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sept. 2007. |
Reference:
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| pp. 242-254, Göteborg, Sweden
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Hyperlink:
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| [Link to the Workshop]
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» Parallelisierung von SAT-basierter Testmustergenerierung
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Author:
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Daniel Tille, Robert Wille, Rolf Drechsler |
| Workshop: |
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21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007) |
Reference:
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| Hamburg, 2007
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Hyperlink:
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| [Link to the Workshop]
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