AMBITIOUS AND AGILE - Institutional Strategy for Advancing Research Strengths at a Mid-sized University
SyDe
Graduate school System Design

Publications

2017
Gökçe Aydos and Görschwin Fey. Empirical results on parity-based soft error detection with software-based retry. Microprocessors and Microsystems (MICPRO), 48:62-68, 2017.
Mehran Goli, Jannis Stoppe, and Rolf Drechsler. Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. In Design, Automation and Test in Europe (DATE), pages 630-633, 2017.
Tino Flenker and Görschwin Fey. Mapping abstract and concrete hardware models for design understanding. In Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 20-25, 2017.
Tino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, and Matteo Sonza Reorda. Towards making fault injection on abstract models a more accurate tool for predicting RT-level effects. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 533-538, 2017.
Sebastian Huhn, Stephan Eggersglüß, and Rolf Drechsler. Reconfigurable TAP controllers with embedded compression for large test data volume. In IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2017.
Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, and Lutz Mädler. Exploring superior structural materials using multi-objective optimization and formal techniques. In 6th IEEE International Symposium on Embedded Computing & System Design (ISED), pages 13-17, 2017.
Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, and Rolf Drechsler. Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. In IEEE Design, Automation and Test in Europe (DATE), pages 578-583, 2017.
Sebastian Huhn, Stefan Frehse, Robert Wille, and Rolf Drechsler. Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. In 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pages 182-187, 2017.
Pablo Gonz'alez de Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, and Pablo S'anchez Espeso. Towards a verification flow across abstraction levels verifying implementations against their formal specification. IEEE Trans. on CAD of Integrated Circuits and Systems, 36(3):475-488, 2017.
Rehab Massoud, Jannis Stoppe, Daniel Große, and Rolf Drechsler. Semi-formal cycle-accurate temporal execution traces reconstruction. In International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS), pages 335-351, 2017.
Arun Chandrasekharan, Daniel Große, and Rolf Drechsler. Yise - a novel framework for boolean networks using Y-inverter graphs. In ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), 2017.
Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. In Forum on Specification and Design Languages (FDL), 2017.
Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Early SoC security validation by VP-based static information flow analysis. In International Conference on Computer-Aided Design (ICCAD), 2017.
Arun Chandrasekharan, Daniel Große, and Rolf Drechsler. ProACt: a processor for high performance on-demand approximate computing. In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 463-466, 2017.
Saman Fröhlich, Daniel Große, and Rolf Drechsler. Error bounded exact BDD minimization in approximate computing. In International Symposium on Multi-Valued Logic (ISMVL), pages 254-259, 2017.
Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, and Rolf Drechsler. Data flow testing for virtual prototypes. In Design, Automation and Test in Europe (DATE), pages 380-385, 2017.
Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, and Rolf Drechsler. Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. In ASP Design Automation Conf. (ASP-DAC), pages 57-62, 2017.

2016
Gökçe Aydos and Görschwin Fey. Exploiting error detection latency for parity-based soft error detection. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 3-8, 2016.
Mehran Goli, Jannis Stoppe, and Rolf Drechsler. AIBA: an automated intra-cycle behavioral analysis for SystemC-based design exploration. In IEEE International Conference on Computer Design (ICCD), pages 360-363, 2016.
Tino Flenker and Görschwin Fey. Matching abstract and concrete hardware models for design understanding. In Design Automation for Understanding Hardware Designs (DUHDe), 2016.
Malgorzata Goldhoorn and Ronny Hartanto. Enhancing Object Detection by using Probabilistic Spatial-Semantic Knowledge. Journal of Computers, 12(01), 2016.
Sebastian Huhn, Stephan Eggersglüß, and Rolf Drechsler. VecTHOR: Low-cost compression architecture for IEEE-1149.1-compliant TAP controllers. In 21st IEEE European Test Symposium (ETS), pages 1-6, 2016.
Sebastian Huhn, Stephan Eggersglüß, and Rolf Drechsler. Leichtgewichtige Datenkompressions-Architektur für IEEE-1149.1-kompatible Testschnittstellen. In 28. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ), 2016.
Jan Peleska, Wen-ling Huang, and Felix Hübner. A Novel Approach to HW/SW Integration Testing of Route-Based Interlocking System Controllers. In Thierry Lecomte, Ralf Pinger, and Alexander Romanovsky, editors, Reliability, Safety, and Security of Railway Systems. Modelling, Analysis, Verification, and Certification, number 9707 in Lecture Notes in Computer Science, pages 32-49. Springer International Publishing, June 2016.
Judith Peters, Nils Przigoda, Robert Wille, and Rolf Drechsler. Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models. In International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 78-84, 2016.
Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, and Rolf Drechsler. Frame conditions in symbolic representations of UML/OCL models. In International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 65-70, 2016.
Nils Przigoda, Mathias Soeken, Robert Wille, and Rolf Drechsler. Verifying the structure and behavior in UML/OCL models using satisfiability solvers. IET Cyper-Phys. Syst.: Theory & Appl., 1(1):49-59, 2016.
Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, and Rolf Gogolla, Martin Drechsler. Integrating an SMT-based Model Finder into USE. In Workshop on Model-Driven Engineering, Verification and Validation, pages 40-45, 2016.
Nils Przigoda, Robert Wille, and Rolf Drechsler. Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding. In International Conference on Model Driven Engineering Languages and Systems (MoDELS), 2016.
Nils Przigoda, Gerhard Dueck, Robert Wille, and Rolf Drechsler. Fault Detection in Parity Preserving Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), pages 44-49, 2016.
Dennis Schüthe, Felix Wenk, and Udo Frese. Dynamics calibration of a redundant flexible joint robot based on gyroscopes and encoders. In ICINCO 2016 - 13th International Conference on Informatics in Control, Automation and Robotics, 2016. (accepted, best paper candidate).
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, and Rolf Drechsler. Approximate BDD optimization with prioritized ε-preferred evolutionary algorithm. In Genetic and Evolutionary Computation Conference (GECCO), pages 79-80, 2016.
Saeideh Shirinzadeh, Mathias Soeken, and Rolf Drechsler. Multi-objective BDD optimization for RRAM based circuit design. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 46-51, 2016.
Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amaru, Rolf Drechsler, and Giovanni De Micheli. An MIG-based compiler for programmable logic-in-memory architectures. In Design Automation Conf. (DAC), pages 117:1-117:6, 2016.
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, and Rolf Drechsler. Fast logic synthesis for rram-based in-memory computing using majority-inverter graphs. In Design, Automation and Test in Europe (DATE), pages 948-953, 2016.
Niels Thole, Lorena Anghel, and Görschwin Fey. A hybrid algorithm to conservatively check the robustness of circuits. In Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2016. (accepted).
Amr Sayed Ahmed, Daniel Große, Mathias Soeken, and Rolf Drechsler. Equivalence checking using Gröbner bases. In Int'l Conf. on Formal Methods in CAD (FMCAD), pages 169-176, 2016.
Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. In Forum on Specification and Design Languages (FDL), pages 1-8, 2016.
Daniel Große, Hoang M. Le, Muhammad Hassan, and Rolf Drechsler. Guided lightweight software test qualification for IP integration using virtual prototypes. In Int'l Conf. on Comp. Design (ICCD), pages 606-613, 2016.
Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Compiled symbolic simulation for SystemC. In International Conference on Computer-Aided Design (ICCAD), pages 52:1-52:8, 2016.
Arun Chandrasekharan, Mathias Soeken, Daniel Große, and Rolf Drechsler. Approximation-aware rewriting of AIGs for error tolerant applications. In International Conference on Computer-Aided Design (ICCAD), pages 83:1-83:8, 2016.
Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. ParCoSS: efficient parallelized compiled symbolic simulation. In Computer Aided Verification (CAV), pages 177-183, 2016.
Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, and Görschwin Fey. metaSMT: Focus on your application not on solver integration. Software Tools for Technology Transfer (STTT), pages 1-17, 2016.
Arun Chandrasekharan, Mathias Soeken, Daniel Große, and Rolf Drechsler. Precise error determination of approximated components in sequential circuits with model checking. In Design Automation Conf. (DAC), pages 129:1-129:6, 2016.
Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, and Rolf Drechsler. Formal verification of integer multipliers by combining Gröbner basis with logic reduction. In Design, Automation and Test in Europe (DATE), pages 1048-1053, 2016. (Best paper candidate).
Hoang M. Le, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Towards formal verification of real-world SystemC TLM peripheral models - a case study. In Design, Automation and Test in Europe (DATE), pages 1160-1163, 2016.
Arun Chandrasekharan, Daniel Große, Mathias Soeken, and Rolf Drechsler. Symbolic error metric determination for approximate computing. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 75-76, 2016.
Mathias Soeken, Daniel Große, Arun Chandrasekharan, and Rolf Drechsler. BDD minimization for approximate computing. In ASP Design Automation Conf. (ASP-DAC), pages 474-479, 2016.

2015
Gökçe Aydos and Görschwin Fey. Parity-based soft error detection with software-based retry vs. triplication-based soft error correction - an analytical comparison on a flash-based FPGA architecture. In Douglas Cunningham, Petra Hofstedt, Klaus Meer, and Ingo Schmitt, editors, INFORMATIK 2015, volume P-246 of Lecture Notes in Informatics (LNI), pages 1415-1429. Gesellschaft für Informatik, 2015.
Gökçe Aydos and Görschwin Fey. Empirical results on parity-based soft error detection with software-based retry. In Nordic Circuits and Systems Conference (NORCAS), Oct 2015.
Gökçe Aydos and Görschwin Fey. In-circuit error detection with software-based error correction - an alternative to TMR. In SyDe Summer School, pages 272-274. Springer, 2015.
Tino Flenker, André Sülflow, and Görschwin Fey. Diagnostic tests and diagnosis for delay faults using path segmentation. In Asian Test Symposium (ATS), pages 145-150, 2015.
Malgorzata Goldhoorn and Frank Kirchner. Semantic object recognition based on qualitative probabilistic spatial relations. In Formal Modeling and Verification of Cyber-Physical Systems, pages 278-280. Springer, 2015.
Matthias Goldhoorn and Frank Kirchner. Constraint-based handling of component networks. In Formal Modeling and Verification of Cyber-Physical Systems, pages 281-283. Springer, 2015.
Christoph Hilken, Jan Peleska, and Robert Wille. A unified formulation of behavioral semantics for SysML models. In International Conference on Model-Driven Engineering and Software Development, 2015.
Christoph Hilken and Jan Peleska. Model-based testing against complex sysml models. In SyDe Summer School, pages 284-286. Springer, 2015.
Felix Hübner and Jan Peleska. Integrated model-based testing and model checking with the benefits of equivalence partition testing. In Formal Modeling and Verification of Cyber-Physical Systems, pages 287-289. Springer, 2015.
Felix Hübner, Wen-ling Huang, and Jan Peleska. Experimental Evaluation of a Novel Equivalence Class Partition Testing Strategy. In Jasmin Christian Blanchette and Nikolai Kosmatov, editors, Tests and Proofs, number 9154 in Lecture Notes in Computer Science, pages 155-172. Springer International Publishing, July 2015.
Nils Przigoda, Robert Wille, and Rolf Drechsler. Analyzing Inconsistencies in UML/OCL Models. Journal of Circuits, Systems and Computers, 25(03):1-21, 2015.
Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, and Rolf Drechsler. Checking Concurrent Behavior in UML/OCL Models. In International Conference on Model Driven Engineering Languages and Systems (MoDELS), pages 176-185, 2015.
Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, and Rolf Drechsler. Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. In Workshop on Model-Driven Engineering, Verification and Validation, volume 1514 of CEUR Workshop Proceedings, pages 44-47, 2015.
Nils Przigoda, Robert Wille, and Rolf Drechsler. Leveraging the Analysis for Invariant Independence in Formal System Models. In Euromicro Conference on Digital System Design (DSD), pages 359-366, 2015.
Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, and Rolf Drechsler. Verification-driven Design Across Abstraction Levels - A Case Study. In Euromicro Conference on Digital System Design (DSD), pages 375-382, 2015.
Nils Przigoda, Robert Wille, and Rolf Drechsler. Contradiction Analysis For Inconsistent UML/OCL Models. In International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pages 1-6, 2015.
Nils Przigoda, Robert Wille, and Rolf Drechsler. Verbesserung der fehlersuche in inkonsistenten formalen modellen. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 165-172, 2015.
Dennis Schüthe and Udo Frese. Optimal control with state and command limits for a simulated ball batting task. In 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), IEEE, pages 3988-3994, 2015.
Dennis Schüthe. Dynamic rebound control and human robot interaction of a ball playing robot. In Formal Modeling and Verification of Cyber-Physical Systems, volume 1, pages 299-301. Springer Vieweg, 2015.
Niels Thole and Görschwin Fey. Formal verification of robustness. In Formal Modeling and Verification of Cyber-Physical Systems, pages 305-307. Springer, 2015.
Niels Thole, Görschwin Fey, and Alberto Garcia-Ortiz. Conservatively analyzing transient faults. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2015.
Niels Thole, Heinz Riener, and Görschwin Fey. Equivalence checking on system level using a priori knowledge. In Proceedings of the IEEE International Symposium on Design and Diagnostics of Electronic Circuits Systems, pages 177-182, April 2015.
Niels Thole, Görschwin Fey, and Alberto Garcia-Ortiz. Analyzing an set at gate level using a conservative approach. In Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2015.
Felix Wenk and Udo Frese. Pose and posture estimation using inertial sensor data. In Formal Modeling and Verification of Cyber-Physical Systems, pages 308-310. Springer, 2015.
Felix Wenk and Udo Frese. Posture from motion. In Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS 2015), pages 280-285, 2015.
Mehdi Dehbashi and Görschwin Fey. Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocessors and Microsystems (MICPRO), 39(3):157-166, 2015.
Melanie Diepenbeck. Completing Behaviour Driven Development for Testing and Verification. PhD thesis, University of Bremen, 2015.
Judith Peters. Exploiting MARTE/CCSL in Modern Design Flows. PhD thesis, University of Bremen, 2015.
Judith Peters and Rolf Drechsler. Analyzing and simulating time descriptions from UML/MARTE CCSL. In Formal Modeling and Verification of Cyber-Physical Systems, pages 293-295. Springer, 2015.
Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, and Rolf Drechsler. A Generic Representation of CCSL Time Constraints for UML/MARTE Models. In The 52st Annual Design Automation Conference 2015, DAC '15, San Francisco, CA, USA, June 7-11, 2015, pages 122:1-122:6, 2015.
Julia Seiter and Rolf Drechsler. Development of consistent formal models. In Formal Modeling and Verification of Cyber-Physical Systems, 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015, pages 302-304, 2015.
Julia Seiter. Formal Model Refinement. From Specification to Implementation. PhD thesis, University of Bremen, 2015.
Eleonora Schönborn, Robert Wille, and Rolf Drechsler. Quo Vadis, Reversible Circuit Design? Towards Scaling Design and Synthesis of Reversible Circuits. In Reed-Muller 2015 Workshop, Waterloo, Canada, May 18-20, 2015.
Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, and Rolf Drechsler. BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits. In 28th International Conference on VLSI Design, VLSID 2015, Bengaluru, India, January 3-7, 2015, pages 435-440. IEEE, 2015.
Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, and Rolf Drechsler. Recurrence relations revisited: Scalable verification of bit level multiplier circuits. In IEEE Annual Symposium on VLSI (ISVLSI), pages 1-6, 2015.
Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, and Rolf Drechsler. Ensuring safety and reliability of ip-based system design - a container approach. In IEEE International Symposium on Rapid System Protoyping (RSP), 2015.

2014
Malgorzata Goldhoorn and Ronny Hartanto. Semantic Perception using Spatial Potential Fields. In In The 9th International Workshop on Cognitive Robotics (CogRob-2014) of the 21st European Conference on Artificial Intelligence (ECAI-2014), Prague, Czech Republic, 18-22 August, 2014, 2014.
Malgorzata Goldhoorn and Ronny Hartanto. Semantic labelling of 3D point clouds using spatial object constraints. In In Special Session on Active Robot Vision (WARV 2014) of the 9th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP-2014), Lisbon, Portugal, 05-09 January, 2014. IEEE Computer Society, 2014.
Matthias Goldhoorn and Sylvain Joyeux. Extension of a plan-based component manager for real time adaptation. In ISR/Robotik 2014; 41st International Symposium on Robotics; Proceedings of, pages 1-6. VDE, 2014.
Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, and Rolf Drechsler. Verifying consistency between activity diagrams and their corresponding ocl contracts. In Forum on specification & Design Languages (FDL), 2014.
Cécile Braunstein, Anne E. Haxthausen, Wen-ling Huang, Felix Hübner, Jan Peleska, Uwe Schulze, and Linh Vu Hong. Complete Model-Based Equivalence Class Testing for the ETCS Ceiling Speed Monitor. In Stephan Merz and Jun Pang, editors, Formal Methods and Software Engineering, number 8829 in Lecture Notes in Computer Science, pages 380-395. Springer International Publishing, January 2014.
Dennis Schüthe and Udo Frese. Task level optimal control of a simulated ball batting robot. In Joaquim Filipe, Oleg Gusikhin, Kurosh Madani, and Jurek Sasiadek, editors, ICINCO 2014 - 11th International Conference on Informatics in Control, Automation and Robotics, volume 2, pages 45-56. SCITEPRESS, 2014.
Niels Thole and Görschwin Fey. Equivalence checking on system level using stepwise induction. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pages 197-200, 2014.
Mehdi Dehbashi and Görschwin Fey. Debug Automation from Pre-Silicon to Post-Silicon. Springer, 2015.
Mehdi Dehbashi and Görschwin Fey. Debug automation for synchronization bugs at RTL. In VLSI Design Conference, pages 44-49, 2014.
Mehdi Dehbashi and Görschwin Fey. Transaction-based online debug for NoC-based multiprocessor SoCs. In Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP), pages 400-404, 2014.
Mehdi Dehbashi and Görschwin Fey. SAT-based speedpath debugging using waveforms. In IEEE European Test Symposium (ETS), pages 63-68, 2014.
Mehdi Dehbashi and Görschwin Fey. Debug automatisierung für logische schaltungen unter zeitvariation mittels waveforms. In GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2014.
Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, and Rolf Drechsler. Behaviour driven development for tests and verification. In Martina Seidl and Nikolai Tillmann, editors, International Conference on Tests and Proofs, volume 8570 of Lecture Notes in Computer Science, pages 61-77. Springer International Publishing, 2014.
Julia Seiter, Robert Wille, Ulrich Kühne, and Rolf Drechsler. Automatic refinement checking for formal system models. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pages 1-8, 2014.
Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, and Rolf Drechsler. Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines. In IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, April 23-25, 2014, pages 129-134. IEEE, 2014.
Rolf Drechsler and Ulrich Kühne. Safe ip integration using container modules. In Electronic System Design (ISED), pages 1-4, 2014.

2013
Mehdi Dehbashi. Debug Automation from Pre-Silicon to Post-Silicon. PhD thesis, University of Bremen, 2013.
Mehdi Dehbashi, Andre Sülflow, and Görschwin Fey. Automated design debugging in a testbench-based verification environment. Microprocessors and Microsystems (MICPRO), 37(2):206-217, 2013.
Mehdi Dehbashi and Görschwin Fey. Debug automation for logic circuits under timing variations. IEEE Design and Test of Computers (DT), 30(6):60-69, 2013.
Mehdi Dehbashi and Görschwin Fey. Efficient automated speedpath debugging. In IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 48-53, 2013.
Mehdi Dehbashi and Görschwin Fey. Towards debug automation for timing bugs at RTL. In GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2013.
Melanie Diepenbeck, Mathias Soeken, Daniel Große, and Rolf Drechsler. Towards automatic scenario generation from coverage information. In Proceedings of the International Workshop on Automation of Software Test (AST), pages 82-88, May 2013.
Julia Seiter, Robert Wille, Mathias Soeken, and Rolf Drechsler. Determining relevant model elements for the verification of UML/OCL specifications. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pages 1189-1192, 2013.

2012
Mehdi Dehbashi and Görschwin Fey. Automated debugging from pre-silicon to post-silicon. In IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 324-329, 2012.
Mehdi Dehbashi and Görschwin Fey. Automated post-silicon debugging of failing speedpaths. In Asian Test Symposium (ATS), pages 13-18, 2012.
Mehdi Dehbashi and Görschwin Fey. Application of timing variation modeling to speedpath diagnosis. In System, Software, SoC and Silcon Debug Conference (S4D), pages 34-37, 2012.
Mehdi Dehbashi and Görschwin Fey. Automated debugging from pre-silicon to post-silicon. In GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2012.
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, and Anand Raghunathan. Functional analysis of circuits under timing variations. In IEEE European Test Symposium (ETS), page 177, 2012.
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, and Anand Raghunathan. Functional analysis of circuits under timing variations. In edaWorkshop, pages 45-50, 2012.
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, and Anand Raghunathan. On modeling and evaluation of logic circuits under timing variations. In EUROMICRO Symposium on Digital System Design (DSD), pages 431-436, 2012.
Melanie Diepenbeck, Mathias Soeken, Daniel Große, and Rolf Drechsler. Behavior driven development for circuit design and verification. In Proceedings of the International Workshop on High Level Design Validation and Test Workshop (HLDVT), pages 9-16, Nov 2012.
Julia Seiter, Mathias Soeken, Robert Wille, and Rolf Drechsler. Property checking of quantum circuits using quantum multiple-valued decision diagrams. In Reversible Computation, 4th International Workshop, RC 2012, Copenhagen, Denmark, July 2-3, 2012. Revised Papers, pages 183-196, 2012.