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31. / / - Workshop

Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2019)

24. - 26. Februar 2019 | Prien am Chiemsee


Programm

Sonntag, 24. Februar 2019

17:00 - 20:00 Registrierung
18:00 - 20:00 Abendessen Yachthotel, Raum Herreninsel
20:00 - 21:30 Öffentliche Sitzung der GI/GMM/ITG-Fachgruppe
"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Yachthotel, Raum Herreninsel

Montag, 25. Februar 2019

8:30 - 9:00 Registrierung
Yachthotel, Raum Herreninsel
9:00 - 10:00 Eröffnung

Keynote 1:
Moderation: N.N.

Chasing the Robo-Taxi Dream
Rakshith Amarnath, Robert Bosch GmbH
Yachthotel, Raum Herreninsel
10:00 - 10:30 Kaffeepause Yachthotel, Raum Herreninsel
10:30 - 12:00

1

Session 1: Testarchitektur und Kodierung
Moderation: N.N.


A Hybrid Space Compactor for Varying X-Rates
Mohammad Urf Maaz, Alexander Sprenger und Sybille Hellebrand
Universität Paderborn

Modifizierter DEC/TED BCH-Code zur schnellen Decodierung
Paul-Patrick Nordmann und Michael Goessel
Universität Potsdam

Enhanced Embedded Test Compression Technique For Processing Incompressible Test Patterns
Sebastian Huhn, Stephan Eggersglüß und Rolf Drechsler
Universität Bremen, DFKI GmbH, Mentor, A Siemens Business
Yachthotel, Raum Herreninsel
12:00 - 13:30 Mittagessen Yachthotel, Raum Herreninsel
13:30 - 15:00

2

Session 2: Zuverlässigkeit und Teststabilität
Moderation: N.N.

SPICE-based SET Pulse Width Model
Marko Andjelkovic, Milos Krstic und Rolf Kraemer
IHP GmbH

IR-drop Prediction of Test Patterns Using Parasitic Elements
Harshad Dhotre, Rolf Drechsler und Stephan Eggersglüß
Universität Bremen, DFKI GmbH, Mentor, A Siemens Business

Messverfahren zur HF-Charakterisierung des Crosstalks verschiedener Halbleitertechnologien
Bjoern Bieske, Dagmar Kirsten, Andreas Ott und Michael Frey
IMMS GmbH, X-Fab GmbH, Melexis GmbH
Yachthotel, Raum Herreninsel
15:00 - 16:00 Kaffeepause und Postersession

Evaluate Your Test-Program's Performance - A Virtual Tester for Industrial Needs
Sebastian Pointner, Oliver Frank, Christoph Hazott, Robert Wille
JK Universität Linz, Infineon Technologies Austria

Implementation of a CIJTAG network
Rene Krenz-Baath
Hochschule Hamm-Lippstadt

Toward consistent circuit-level aging simulations in different EDA environments
Fabio Alberto Velarde Gonzalez, Kay-Uwe Giering, André Lange, Insaf Lahbib und Sonja Crocoll
Fraunhofer IIS-EAS, X-Fab GmbH

Solder Fatigue Electrical Test Analysis
Andreas Aal, Hosea Busse, Rainer Dudek und Rainhold Ordmann
Volkswagen AG, Goepel Electronic GmbH, Fraunhofer ENAS, Continental
Yachthotel, Raum Herreninsel
16:00 - 17:30

3

Session 3: Sicherheit und Netzwerke
Moderation: N.N.

Lightweight Encryption in Reconfigurable Scan Networks
Benjamin Thiemann, Linus Feiten, Pascal Raiola, Bernd Becker und Matthias Sauer
Universität Freiburg, Advantest Europe GmbH

Diagnosing DoS Attacks in NoC-based MPSoCs
Cesar G. Chaves, Siavoosh Payandeh Azad, Thomas Hollstein und Johanna Sepúlveda
Hochschule Frankfurt, Tallinn University, TU München

Towards Formal Verification of Cache Access-based Side-Channel Attacks
Behrad Niazmand, Cezar Reinbrecht, Jaan Raik, Gert Jervan and Johanna Sepúlveda
Tallinn University, Delft University, TU München
Yachthotel, Raum Herreninsel
17:30 - 18:00 Pause
18:00 - 22.00 Abendveranstaltung und Essen N.N.

Dienstag, 26. Februar 2019

9:00 - 10:00 Keynote 2:
Moderation: N.N.

Towards intelligent methods for test and reliability
Jochen Rivoir, Advantest Europe GmbH
- vertreten durch -
Dr. Matthias Sauer, Advantest Europe GmbH
Yachthotel, Raum Herreninsel
10:00 - 10:30 Kaffeepause Yachthotel, Raum Herreninsel
10:30 - 12:00

4

Session 4: Mixed-Signal Test und Machine Learning
Moderation: N.N.

Neural Networks for Monitoring Embedded Devices
Fin Hendrik Bahnsen und Goerschwin Fey
TU Hamburg

Mixed-Signal Assertions versus Machine-Learning as Fault Detection Method in post-silicon verification
Thomas Nirmaier, Manuel Harrant, Benedikt Gruenewald, Juergen Zimmer, Bjoern Eversmann und Georg Pelz
Infineon

Messumgebung zur dynamischen Charakterisierung des Leistungsverbrauchs von Ultra-Low-Power Schaltungen
Marco Reinhard, Alexander Rolapp, Benjamin Saft und Michael Meister
IMMS GmbH
Yachthotel, Raum Herreninsel
12:00 - 12:30 Schlusswort Yachthotel, Raum Herreninsel
12:30 - 13:30 Mittagessen Yachthotel, Raum Herreninsel

Keynote 1:

Rakshith Amarnath, Robert Bosch GmbH
Chasing the Robo-Taxi Dream


Short abstract:
Future automotive computing platforms are a hub for technology integration. In fact, urban automated driving aka Robo-Taxi is becoming the holy grail of autonomous systems safety. This talk paints a picture of the impending challenges regarding safety assurance as the automotive sector evolves from advanced driver assistance towards self-driving Robo-Taxis. I conclude the talk by giving a link to some of the vital ingredients that help engineers make the Robo-Taxi dream a reality.
Short bio:
Rakshith Amarnath comes from the city of Bangalore in India. He has a Masters in Embedded Systems from the Delft University of Technology in Netherlands. He is currently working on dependable computing (e.g. applied for autonomous driving at Bosch Corporate Research) where he is leading a project on assuring software dependability and is also representing Bosch's research topics in the German federal ministry's publicly funded projects.

Keynote 2:

Jochen Rivoir, Advantest Europe GmbH
- vertreten durch -
Dr. Matthias Sauer, Advantest Europe GmbH
Towards intelligent methods for test and reliability


Short abstract:
Moore's law continues to enable more complex or lower cost ICs for an interconnected world of IoT, 5G, AR/VR, Industry 4.0, ADAS, big data analytics, and AI - on which our entire society relies increasingly. Test throughout the value chain will have to ensure unprecedented levels of dependability of the underlying hardware, despite exploding complexity and shortening time-to-market expectations. These challenges call for intelligent automated test solutions that bridge gaps in workflows and value chains. This keynote will talk about these trends, their implications, and propose some ideas with emphasis on post silicon validation and system level test. Hurdles for deployment of machine-learning in test will be discussed, hoping to stimulate further research and collaboration.
Short bio:
Jochen Rivoir ist Advantest Fellow im Applied Research and Venture Team von Advantest. Er arbeitet seit 1985 in Forschung und Entwicklung bei Hewlett-Packard, Agilent, Verigy und jetzt Advantest in Deutschland. Seine berufliche Leidenschaft gilt innovativen generischen Lösungen für Herausforderungen im Bereich Halbleitertest, wobei zunehmend Methoden des machinellen Lernens zur Geltung kommen.

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