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29. / / - Workshop

Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017)

5.-7. März 2017 | ParkInn Hotel, Lübeck


Programm

Sonntag, 5. März 2017

17:00 - 20:00 Registrierung ParkInn, Foyer Pier
18:00 - 20:00 Abendessen ParkInn, Restaurant LaBaracca
20:00 - 21:30 Öffentliche Sitzung der GI/GMM/ITG-Fachgruppe "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" ParkInn, Pier 6

Montag, 6. März 2017

8:30 - 9:00 Registrierung
ParkInn, Foyer Pier
9:00 - 10:00 Eröffnung

Keynote 1:
Moderation: Heinrich T. Vierhaus
BTU Cottbus-Senftenberg
How not to screw up the board/system test with a bad IC-level DFT
Artur Jutman Testonica Lab, Estland
ParkInn, Pier 1-5
10:00 - 10:30 Kaffeepause ParkInn, Foyer Pier
10:30 - 12:00

1

Session 1: Testgenerierung und Diagnose
Moderation: Ilia Polian
Universität Passau

On Enabling Diagnosis for 1-Pin Test Fails in an Industrial Flow
Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen
Infineon Technologies

X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz
Matthias Kampmann, Sybille Hellebrand
Universität Paderborn

On Optimal Power-aware Path Sensitization
Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian
Universität Freiburg, Universität Passau, Kyushu Institute of Technology
ParkInn, Pier 1-5
12:00 - 13:30 Mittagessen ParkInn, Restaurant LaBaracca
13:30 - 14:30

2

Session 2: Test und Messverfahren
Moderation: Wolfgang Hoppe

Charakterisierung und Test von elektrostatischen Energieharvestern - eine neue Schaltungstopologie für exaktere Messungen
Björn Bieske, Gerrit Kropp
IMMS GmbH

Octal-site Testing of a State-of-the-art LTE RF-Transceiver IC
Stephan Fuchs, Robert Weigel
Intel Deutschland, FAU Erlangen-Nürnberg
ParkInn, Pier 1-5
14:30 - 16:00 Kaffeepause und Postersession

ESD Test Integrierter Schaltungen im Betrieb
Timm Ostermann, Manuel Kaufmann
JK Universität Linz

Processor Error Detection Capabilities of Random Programs
Johannes Kohl, Wolfgang Bauer, Jürgen Bäsig, Dietmar Fey, Stefan Rübesam
Technische Hochschule Nürnberg, profichip GmbH

Hoch-zuverlässige schnelle Encoder / Decoder für drahtlose Übertragungssysteme
Heinrich T. Vierhaus, Petr Pfeifer, Davide Dicorato
BTU Cottbus-Senftenberg

Eine Methode zur Verifikation von Mixed-Signal-ASIC
Anselm Breitenreiter, Jesús López, Pedro Reviriego, Daniel González, Milos Krstic
IHP, Arquimea Ingenieria S.L.U., Universidad Antonio de Nebrija, Madrid

Empirical Evaluation of a Formal Conservative Analysis to Prove Robustness under Variability
Niels Thole, Görschwin Fey
Universität Bremen, DLR

A Lightweight Method for Transient Test Power Pattern Analysis for Pattern Selection
Harshad Dhotre, Stephan Eggersglüß
DFKI, Universität Bremen
ParkInn, Foyer Pier
16:00 - 17:30

3

Session 3: Spezifikation, Netzwerke und Speichertest
Moderation: Daniel Tille
Infineon Technologies

Projekt 42: Testspezifikationen programmieren mit Eclipse, Xtext und Xtend
Nico Nebel, Tobias Rall
Robert Bosch GmbH

FSM-based Analysis for Retargeting in IEEE 1687 Networks
Rene Krenz-Baath
Hochschule Hamm-Lippstadt

Analyzing the Effects of Peripheral Circuit Aging of Embedded SRAM Architectures
Josef Kinseher, Leonhard Heiß, Ilia Polian
Intel Deutschland, Universität Passau
ParkInn, Pier 1-5
17:30 - 18:00 Pause
18:00 - 22.00 Abendveranstaltung und Essen Lübecker Altstadt und Ratskeller

Dienstag, 7. März 2017

9:00 - 10:00 Keynote 2:
Moderation: Jürgen Alt
Intel Deutschland
Safety Systems Engineering
Paul Pop
DTU Compute, Technical University of Denmark
ParkInn, Pier 1-5
10:00 - 10:30 Kaffeepause ParkInn, Foyer Pier
10:30 - 12:30

4

Session 4: Fehlertoleranz und Transiente Fehler
Moderation: Matthias Sauer
Universität Freiburg

On-chip-Erkennung von Störungen durch Single Event Upsets
Jan Schat
NXP Semiconductors

Entwurf eines On-Chip-Systems für die Messung der Breite von SET-Pulsen
Marko Andjelkovic, Vladimir Petrovic, Miljana Nenadovic, Gunther Schoof, Milos Krstic, Rolf Krämer
IHP

Korrektur transienter Fehler durch Rollback mit geringem Software-Overhead für Mikrocontroller
Felix Mühlbauer, Mario Schölzel
Universität Potsdam, IHP

Identifizierung fehlerbewahrender Speicherelemente zur Vermeidung der Fehlerakkumulation
Stefan Weidling, Milos Krstic, Michael Gössel
IHP, Universität Potsdam
ParkInn, Pier 1-5
12:30 - 12:45 Schlusswort ParkInn, Pier 1-5
12:45 - 13:45 Mittagessen ParkInn, Restaurant LaBaracca

Keynote 1:

How not to screw up the board/system test with a bad IC-level DFT
Contemporary high-performance system board is a 3D object that may contain dozens of hidden layers, stacked microvias, high density interconnect, with all above not contributing to ease of test and reliability. High-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in case of ubiquitous DDR3 memories. Data transmission rates on the board may be reaching multi-gigabit ranges on a single channel. The success or failure of a board/system test strategy often depends today on the availability of necessary DFT infrastructure on the ICs even as simple as the JTAG, hence, putting the fate of a board test engineer into the hands of an IC designer and EDA companies. The presentation reviews current challenges in board/system test and certain trends in the IC-level DFT, such as new DFT standards, security vs. availability, cost-saving-driven optimizations, backward compatibility with existing tools and standards, etc. from the perspective of board/system test quality, cost and efficiency.

Keynote 2:

Safety Systems Engineering
When a system might harm humans or the environment, decision-makers require pre-release safety assurance evidence that it manages risk acceptably. The conceptual basis for certification is that the pre-release (design-time) evidence anticipates the possible circumstances that can arise from the interaction between the system and the environment, to show that these interactions do not pose an unacceptable risk. Certification is very expensive, and can add a very large development cost overhead. An increasing number of cyber-physical systems are autonomous, cooperative, created by multiple stakeholders, have dynamic system definitions and operate in unpredictable environments. The safety assurance for such systems poses  challenges that are not adequately addressed by existing practices. This talk will present the current state-of-the-art in the area of safety assurance for such cyber-physical systems.

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