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VIS - Verification Interacting with Synthesis  

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Contents  
  • Identification
  • Homepage
  • Observations
  • Classifications
  • Identification

    VIS - Verification Interacting with Synthesis

    Homepage

    http://www-cad.eecs.Berkeley.EDU/~vis/

    Observations

    A system for formal verification, synthesis, and simulation of finite state systems, especially logic circuits. Includes a Verilog HDL front-end

    Classifications

    Development Phases: Verification
    Development Phases: Synthesis
    Development Phases: Simulation

    GDPA Online Last Updated 01.Jan.2002 Updated by Webmaster Last Revised 01.Jan.2002 Revised by Webmaster