184.108.40.206 Specification by Traces
Spezifikation mittels Traces
The Specification of Traces is a formal specification describing the sequences of a program, i. e. the order of individual states or individual operations. The specification is done via the characteristics of these traces.
The Specification of Traces may be applied for the description of the operation behavior on every level of abstraction. This specification also is ideal for the description of sequences of combined programs or automata (e. g. parallelism).
There are interfaces to DVER - Design Verification, PVER - Program Verification and ACC - Analysis of Covert Channels.
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||Basic features of formal methods as a stock-taking of tools and concepts|
||Manual of the conference VDM '90; main emphasis is put on actual topics with regard to the formal specification languages VDM and Z
||Several specification topics, principles and characteristics for a good specification, several specification methods, the application of formal specification techniques in practice are discussed|
||Specification in Z|
||Describes VDM and its basis|
||Several reports on "formal specification and verification"|
||Deals with temporal logic and verification of statements in temporal logic
||Last Updated 01.Jan.2002