Dr. Daniel Grosse

Senior Researcher @ AGRA - University of Bremen
Scientific Coordinator of Graduate School SyDe
Senior Researcher @ DFKI Cyber-Physical Systems

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Research Interests


  • Electronic Design Automation (EDA)
  • Modelling (UML, SystemC, (System)Verilog, VHDL)
  • Virtual Prototpying and Transaction Level Modeling (TLM)
  • Simulation-based verification (UVM, Constrained Random Simulation)
  • Formal verification (Model Checking, Equivalence Checking)
  • Symbolic Computer Algebra (SCA)
  • (Functional) coverage
  • Automated debugging
  • Approximate Computing
  • Algorithms and data structures (SMT, SAT, BDD)
  • New technologies (Reversible Logic, Quantum Computation)

Publications


Diploma Thesis

Dissertation

Books

Book Contributions

Journals

Conferences

Workshops

Others

Professional Service (selected)

Published Software

  • Formal verification solutions based on Symbolic Computer Algebra (SCA) for complex arithmetic circuits. We also provide GenMul a configurable (input size and architecture) generator for multipliers in Verilog. See www.sca-verification.org.
  • RISC-V Virtual Prototype (VP) modeled in SystemC. The VP is open source, TLM2.0 compliant, and has great features like e.g. software debug via Eclipse by integrated GDB support, and runs FreeRTOS. See www.systemc-verification.org/riscv-vp for the github repositories.
  • ESL Verification tools & topics, in particular constrained-random library CRAVE and formal TLM verification methods (SCIVER and SISSI), available at www.systemc-verification.org
  • Symbolic approaches for Approximate Computing, available at www.informatik.uni-bremen.de/agra/ger/maniac.php
  • metaSMT - An Embedded Domain Specific Language for SMT (Satisfiability Modulo Theories), available at www.informatik.uni-bremen.de/agra/eng/metasmt.php and GitHub
  • RevLib: Online-database for benchmarks within the domain of reversible and quantum circuit design, available at www.revlib.org

Contact


Let's get in touch!

+49 421 218 - 63935