[8] B Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. In F. Fummi and R. Wille, editors, Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2016, pages 39-58. Springer, 2018.
[9] B Daniel Große, Hoang M. Le, and Rolf Drechsler. Formal verification of SystemC-based cyber components. In S. Jeschke, C. Brecher, H. Song, and D. B. Rawat, editors, Industrial Internet of Things: Cybermanufacturing Systems, pages 137-167. Springer, 2016.
[10] B Daniel Große, Görschwin Fey, and Rolf Drechsler. Enhanced formal verification flow for circuits integrating debugging and coverage analysis. In R. Ubar, J. Raik, and H. T. Vierhaus, editors, Design and Test Technology for Dependable Systems-on-Chip, pages 119-129. Information Science Reference, 2011.
[11] B Robert Wille, Daniel Große, Finn Haedicke, and Rolf Drechsler. SMT-based stimuli generation in the SystemC verification library. In D. Borrione, editor, Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's: Selected Contributions on Specification, Design, and Verification from FDL 2009, pages 227-244. Springer, 2010.
[12] B Daniel Große. Qualitätsorientierter Entwurfs- und Verifikationsablauf für digitale Systeme. In D. Wagner et al., editor, Ausgezeichnete Informatikdisserationen 2008, volume D-9 of Lecture Notes in Informatics, pages 121-130. Gesellschaft für Informatik, 2009.
[13] B Daniel Große, Robert Wille, Robert Siegmund, and Rolf Drechsler. Debugging contradictory constraints in constraint-based random simulation. In M. Radetzki, editor, Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08, pages 273-290. Springer, 2009.
[14] B Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, and Rolf Drechsler. Sword: A SAT like prover using word level information. In R. Reis, V. Mooney, and P. Hasler, editors, VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip, pages 175-192. Springer, 2009.
[15] B Daniel Große, Hernan Peraza, Wolfgang Klingauf, and Rolf Drechsler. Measuring the quality of a SystemC testbench by using code coverage techniques. In E. Villar, editor, Embedded Systems Specification and Design Languages: Selected contributions from FDL'07, pages 73-86. Springer, 2008.
[16] B Daniel Große, Robert Siegmund, and Rolf Drechsler. Processor verification. In P. Ienne and R. Leupers, editors, Customizable Embedded Processors, pages 281-302. Elsevier, 2006.
[17] B Rolf Drechsler and Daniel Große. System-level validation using formal techniques. In Bashir M. Al-Hashimi, editor, System-on-Chip: Next Generation Electronics, pages 715-745. The IEE, 2006.