[31] B Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, and Rolf Drechsler. Approximation-aware testing for approximate circuits. In ASP-DAC, 2018.
[32] B PDF Arun Chandrasekharan, Daniel Große, and Rolf Drechsler. Yise - a novel framework for boolean networks using Y-inverter graphs. In MEMOCODE, 2017.
[33] B PDF Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. In FDL, 2017.
[34] B PDF Rehab Massoud, Jannis Stoppe, Daniel Große, and Rolf Drechsler. Semi-formal cycle-accurate temporal execution traces reconstruction. In FORMATS, 2017.
[35] B PDF Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Early SoC security validation by VP-based static information flow analysis. In ICCAD, 2017.
[36] B PDF Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, and Rolf Drechsler. An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization. In GECCO, pages 1232-1239, 2017.
[37] B PDF Arun Chandrasekharan, Daniel Große, and Rolf Drechsler. ProACt: a processor for high performance on-demand approximate computing. In GLSVLSI, pages 463-466, 2017.
[38] B PDF Saman Fröhlich, Daniel Große, and Rolf Drechsler. Error bounded exact BDD minimization in approximate computing. In ISMVL, pages 254-259, 2017.
[39] B PDF Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, and Rolf Drechsler. Data flow testing for virtual prototypes. In DATE, pages 380-385, 2017.
[40] B PDF Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, and Rolf Drechsler. Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. In ASP-DAC, pages 57-62, 2017.
[41] B PDF Daniel Große, Hoang M. Le, Muhammad Hassan, and Rolf Drechsler. Guided lightweight software test qualification for IP integration using virtual prototypes. In ICCD, pages 606-613, 2016.
[42] B PDF Amr Sayed-Ahmed, Daniel Große, Mathias Soeken, and Rolf Drechsler. Equivalence checking using Gröbner bases. In FMCAD, pages 169-176, 2016.
[43] B PDF Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. In FDL, pages 1-8, 2016.
[44] B PDF Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Compiled symbolic simulation for SystemC. In ICCAD, pages 52:1-52:8, 2016.
[45] B PDF Arun Chandrasekharan, Mathias Soeken, Daniel Große, and Rolf Drechsler. Approximation-aware rewriting of AIGs for error tolerant applications. In ICCAD, pages 83:1-83:8, 2016.
[46] B PDF Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. ParCoSS: efficient parallelized compiled symbolic simulation. In CAV, pages 177-183, 2016.
[47] B PDF Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, and Rolf Drechsler. Approximate BDD optimization with prioritized ε-preferred evolutionary algorithm. In GECCO, pages 79-80, 2016.
[48] B PDF Arun Chandrasekharan, Mathias Soeken, Daniel Große, and Rolf Drechsler. Precise error determination of approximated components in sequential circuits with model checking. In DAC, pages 129:1-129:6, 2016.
[49] B PDF Amr Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, and Rolf Drechsler. Formal verification of integer multipliers by combining Gröbner basis with logic reduction. In DATE, pages 1048-1053, 2016. (Best paper candidate).
[50] B PDF Hoang M. Le, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Towards formal verification of real-world SystemC TLM peripheral models - a case study. In DATE, pages 1160-1163, 2016.
[51] B PDF Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, and Rolf Drechsler. Quantitative timing analysis of UML activity diagrams using statistical model checking. In DATE, pages 780-785, 2016.
[52] B PDF Mathias Soeken, Daniel Große, Arun Chandrasekharan, and Rolf Drechsler. BDD minimization for approximate computing. In ASP-DAC, pages 474-479, 2016.
[53] B PDF Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Boosting sequentialization-based verification of multi-threaded C programs via symbolic pruning of redundant schedules. In ATVA, pages 228-233, 2015.
[54] B PDF Amr Sayed-Ahmed, Ulrich Kühne, Daniel Große, and Rolf Drechsler. Recurrence relations revisited: Scalable verification of bit level multiplier circuits. In ISVLSI, pages 1-6, 2015.
[55] B PDF Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, and Wolfgang Rosenstiel. Constraint-based platform variants specification for early system verification. In ASP-DAC, pages 800-805, 2014.
[56] B PDF Shuo Yang, Robert Wille, Daniel Große, and Rolf Drechsler. Minimal stimuli generation in simulation-based verification. In DSD, pages 439-444, 2013.
[57] B PDF Hoang M. Le, Daniel Große, Vladimir Herdt, and Rolf Drechsler. Verifying SystemC using an intermediate verification language and symbolic simulation. In DAC, pages 116:1-116:6, 2013.
[58] B PDF Rolf Drechsler, Daniel Große, Hoang M. Le, and André Sülflow. Synchronized debugging across different abstraction levels in system design. In Embedded World Conference, 2013.
[59] B PDF Hoang M. Le, Daniel Große, and Rolf Drechsler. Scalable fault localization for SystemC TLM designs. In DATE, pages 35-38, 2013.
[60] B PDF Hoang M. Le, Daniel Große, and Rolf Drechsler. From requirements and scenarios to ESL design in SystemC. In ISED, pages 183-187, 2012.
[61] B PDF Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, and Volkan Esen. The system verification methodology for advanced TLM verification. In CODES+ISSS, pages 313-322, 2012.
[62] B PDF Finn Haedicke, Hoang M. Le, Daniel Große, and Rolf Drechsler. CRAVE: An advanced constrained random verification environment for SystemC. In SoC, pages 1-7, 2012.
[63] B PDF Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, J. Seiter, Mathias Soeken, and Robert Wille. Completeness-driven development. In ICGT, pages 38-50, 2012.
[64] B PDF Marc Michael, Daniel Große, and Rolf Drechsler. Localizing features of ESL models for design understanding. In FDL, pages 120-125, 2012.
[65] B PDF Shuo Yang, Robert Wille, Daniel Große, and Rolf Drechsler. Coverage-driven stimuli generation. In DSD, pages 525-528, 2012.
[66] B PDF Finn Haedicke, Daniel Große, and Rolf Drechsler. A guiding coverage metric for formal verification. In DATE, pages 617-622, 2012.
[67] B PDF Marc Michael, Daniel Große, and Rolf Drechsler. Analyzing dependability measures at the Electronic System Level. In FDL, pages 1-8, 2011.
[68] B PDF Mohamed Bawadekji, Daniel Große, and Rolf Drechsler. TLM protocol compliance checking at the electronic system level. In DDECS, pages 435-440, 2011.
[69] B PDF Robert Wille, Mathias Soeken, Daniel Große, E. Schönborn, and Rolf Drechsler. Designing a risc cpu in reversible logic. In ISMVL, pages 170-175, 2011.
[70] B PDF Daniel Große, M. Groß, Ulrich Kühne, and Rolf Drechsler. Simulation-based equivalence checking between SystemC models at different levels of abstraction. In GLSVLSI, pages 223-228, 2011.
[71] B PDF Daniel Große, Hoang M. Le, and Rolf Drechsler. Proving transaction and system-level properties of untimed SystemC TLM designs. In MEMOCODE, pages 113-122, 2010.
[72] B PDF Robert Wille, Daniel Große, Finn Haedicke, and Rolf Drechsler. SMT-based stimuli generation in the SystemC verification library. In FDL, pages 1-6, 2009.
[73] B PDF André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, and Rolf Drechsler. WoLFram - a word level framework for formal verification. In RSP, pages 11-17, 2009.
[74] B PDF Daniel Große, Robert Wille, Ulrich Kühne, and Rolf Drechsler. Contradictory antecedent debugging in bounded model checking. In GLSVLSI, pages 173-176, 2009.
[75] B PDF Robert Wille, Daniel Große, D. Michael Miller, and Rolf Drechsler. Equivalence checking of reversible circuits. In ISMVL, pages 324-330, 2009.
[76] B PDF Ulrich Kühne, Daniel Große, and Rolf Drechsler. Property analysis and design understanding. In DATE, pages 1246-1249, 2009.
[77] B PDF Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, and Rolf Drechsler. Debugging of Toffoli networks. In DATE, pages 1284-1289, 2009.
[78] B PDF Robert Wille, Daniel Große, Gerhard W. Dueck, and Rolf Drechsler. Reversible logic synthesis with output permutation. In VLSI Design, pages 189-194, 2009.
[79] B PDF Daniel Große, Robert Wille, Robert Siegmund, and Rolf Drechsler. Contradiction analysis for constraint-based random simulation. In FDL, pages 130-135, 2008.
[80] B PDF Robert Wille, Daniel Große, Mathias Soeken, and Rolf Drechsler. Using higher levels of abstraction for solving optimization problems by boolean satisfiability. In ISVLSI, pages 411-416, 2008.
[81] B PDF Daniel Große, Robert Wille, Gerhard W. Dueck, and Rolf Drechsler. Exact synthesis of elementary quantum gate circuits for reversible functions with don't cares. In ISMVL, pages 214-219, 2008.
[82] B PDF Robert Wille, Daniel Große, L. Teuber, Gerhard W. Dueck, and Rolf Drechsler. RevLib: an online resource for reversible functions and reversible circuits. In ISMVL, pages 220-225, 2008. RevLib is available at http://www.revlib.org.
[83] B PDF Robert Wille, Hoang M. Le, Gerhard W. Dueck, and Daniel Große. Quantified synthesis of reversible logic. In DATE, pages 1015-1020, 2008.
[84] B PDF Robert Wille and Daniel Große. Fast exact Toffoli network synthesis of reversible logic. In ICCAD, pages 60-64, 2007.
[85] B PDF Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, and Rolf Drechsler. Sword: A SAT like prover using word level information. In VLSI-SoC, pages 88-93, 2007.
[86] B PDF Daniel Große, Hernan Peraza, Wolfgang Klingauf, and Rolf Drechsler. Measuring the quality of a SystemC testbench by using code coverage techniques. In FDL, pages 146-151, 2007. (Best paper award).
[87] B PDF Ulrich Kühne, Daniel Große, and Rolf Drechsler. Improving the quality of bounded model checking by means of coverage estimation. In ISVLSI, pages 165-170, 2007.
[88] B PDF Mahsan Amoui, Daniel Große, Mitchell A. Thornton, and Rolf Drechsler. Evaluation of toggle coverage for mvl circuits specified in the SystemVerilog HDL. In ISMVL, page 50 (6 pages), 2007.
[89] B PDF Daniel Große, Rüdiger Ebendt, and Rolf Drechsler. Improvements for constraint solving in the SystemC verification library. In GLSVLSI, pages 493-496, 2007.
[90] B PDF Daniel Große, Xiaobo Chen, Gerhard W. Dueck, and Rolf Drechsler. Exact SAT-based Toffoli network synthesis. In GLSVLSI, pages 96-101, 2007.
[91] B PDF Daniel Große, Ulrich Kühne, and Rolf Drechsler. Estimating functional coverage in bounded model checking. In DATE, pages 1176-1181, 2007.
[92] B PDF Daniel Große, Ulrich Kühne, and Rolf Drechsler. Hw/sw co-verification of embedded systems using bounded model checking. In GLSVLSI, pages 43-48, 2006.
[93] B PDF Görschwin Fey, Daniel Große, and Rolf Drechsler. Avoiding false negatives in formal verification for protocol-driven blocks. In DATE, pages 1225-1226, 2006.
[94] B PDF Daniel Große and Rolf Drechsler. Acceleration of SAT-based iterative property checking. In CHARME, pages 349-353, 2005.
[95] B PDF Daniel Große and Rolf Drechsler. CheckSyC: An efficient property checker for RTL SystemC designs. In ISCAS, pages 4167-4170, 2005.
[96] B PDF Jan Peleska, Daniel Große, Anne E. Haxthausen, and Rolf Drechsler. Automated verification for train control systems. In Formal Methods for Automation and Safety in Railway and Automotive Systems, pages 252-265, 2004.
[97] B PDF Daniel Große and Rolf Drechsler. Checkers for SystemC designs. In MEMOCODE, pages 171-178, 2004.
[98] B PDF Daniel Große, Rolf Drechsler, Lothar Linhard, and Gerhard Angst. Efficient automatic visualization of SystemC designs. In FDL, pages 646-657, 2003.
[99] B PDF Daniel Große and Rolf Drechsler. Formal verification of LTL formulas for SystemC designs. In ISCAS, pages V:245-V:248, 2003.
[100] B PDF Daniel Große, Görschwin Fey, and Rolf Drechsler. Modeling multi-valued circuits in SystemC. In ISMVL, pages 281-286, 2003.
[101] B PDF Rolf Drechsler and Daniel Große. Reachability analysis for formal verification of SystemC. In DSD, pages 337-340, 2002.
[102] B Frank Schmiedle, Nicole Drechsler, Daniel Große, and Rolf Drechsler. Priorities in multi-objective optimization for genetic programming. In GECCO, pages 129-136, 2001.
[103] B Frank Schmiedle, Daniel Große, Rolf Drechsler, and Bernd Becker. Too much knowledge hurts: Acceleration of genetic programs for learning heuristics. In Int'l Conference on Computational Intelligence (Fuzzy Days), volume 2206 of LNCS, pages 479-491, 2001.
[104] B Nicole Drechsler, Frank Schmiedle, Daniel Große, and Rolf Drechsler. Heuristic learning based on genetic programming. In European Conference on Genetic Programming, volume 2038 of LNCS, pages 1-10. Springer, 2001.