[17] B Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, and Görschwin Fey. metaSMT: Focus on your application not on solver integration. STTT, pages 1-17, 2016.
[18] B Daniel Große, Görschwin Fey, and Rolf Drechsler. Enhanced formal verification flow for circuits integrating debugging and coverage analysis. Electronic Communication of the European Association of Software Science and Technology, 62, 2013.
[19] B Hoang M. Le, Daniel Große, and Rolf Drechsler. Automatic TLM fault localization for SystemC. TCAD, 31(8):1249-1262, August 2012.
[20] B Robert Wille, Daniel Große, D. Michael Miller, and Rolf Drechsler. Equivalence checking of reversible circuits. Multiple-Valued Logic and Soft Computing, 19(4):361-378, 2012.
[21] B Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, and Rolf Drechsler. Debugging reversible circuits. Integration, the VLSI Journal, 44(1):51-61, January 2011.
[22] B Ulrich Kühne, Daniel Große, and Rolf Drechsler. Towards fully automatic synthesis of embedded software. IEEE Embedded Systems Letters, 2(3):53-57, September 2010.
[23] B Bernd Scholz-Reiter, Michael Lütjen, Carmen Ruthenbeck, Florian Harjes, Rolf Drechsler, and Daniel Große. Formale Verifikation von logistischen Prozessmodellen. ERP Management, 5(4):44-47, 2009.
[24] B Daniel Große, Robert Wille, Gerhard W. Dueck, and Rolf Drechsler. Exact multiple control Toffoli network synthesis with SAT techniques. TCAD, 28(5):703-715, 2009.
[25] B Daniel Große, Robert Wille, Gerhard W. Dueck, and Rolf Drechsler. Exact synthesis of elementary quantum gate circuits. Multiple-Valued Logic and Soft Computing, 15(4):283-300, 2009.
[26] B Daniel Große, Ulrich Kühne, and Rolf Drechsler. Analyzing functional coverage in bounded model checking. TCAD, 27(7):1305-1314, 2008.
[27] B Daniel Große and Rolf Drechsler. BDD-based verification of scalable designs. Facta Universitatis. Series: Electronics and Energetics, 20(3):367-379, 2007.
[28] B Rolf Drechsler and Daniel Große. System level validation using formal techniques. IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends, 152(3):393-406, May 2005.
[29] B Daniel Große and Rolf Drechsler. Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it+ti, 4:219-226, 2003.
[30] B Frank Schmiedle, Nicole Drechsler, Daniel Große, and Rolf Drechsler. Heuristic learning based on genetic programming. Genetic Programming and Evolvable Machines, 3:363-388, 2002.