[146] B Daniel Große (organizer). Automatic firmware design for application-specific electronic systems: Opportunities, challenges and solutions, Speaker: Daniel Große, Joscha Benz, Vladimir Herdt, Martin Dittrich. In Tutorial at DVCon Europe, 2017.
[147] B Daniel Große (panelist). The WHAT? and WHY? of high-level languages in designing and verifying complex integrated systems - Lets take a formal perspective. In Panel at Forum on specification & Design Languages, 2017.
[148] B Stephan Gerth and Daniel Große. UVM-SystemC goes random - introducing CRAVE in UVM-SystemC. In Tutorial at DVCon Europe, 2016.
[149] B Daniel Große (organizer). Reliability and safety in VP-based embedded system development, Speaker: Vladimir Herdt, Bogdan-Andrei Tabacaru. In Special Session at Forum on specification & Design Languages, 2016.
[150] B Daniel Große. Circuit design: Slip schedule or automate debug. In DVClub Shanghai: Making Verification Debug More Efficient, 2014.
[151] B Daniel Große. Circuit design: Slip schedule or automate debug. In ISMVL, 2014.
[152] B Daniel Große, Finn Haedicke, Hoang M. Le, and Rolf Drechsler. An advanced constrained random verification environment for SystemC. In 24. European SystemC User's Group Meeting (ESCUG), 2011.
[153] B Daniel Große and Frank Schirrmeister (organizer). ESL HW/SW verification: A reality check, Speaker: Matthias Bauer, Viraphol Chaiyakul, Alan Gatherer, Sandeep Shukla, Daniel Kroening. In Panel at Design Automation Conference (DAC), 2011.
[154] B Daniel Große, Hoang M. Le, and Rolf Drechsler. Formal verification of abstract SystemC models. In Bernd Becker, Valeria Bertacco, Rolf Drechsler, and Masahiro Fujita, editors, Algorithms and Applications for Next Generation SAT Solvers, number 09461 in Dagstuhl Seminar Proceedings, 2010.
[155] B Oliver Bringmann, Wolfgang Ecker, Volkan Esen, Erhard Fehlauer, Daniel Große, Christoph Kuznik, Jan-Hendrik Oetjens, and Andreas von Schwerin. State-of-the-art and challenges in ESL-verification. In Full-Day Tutorial at Design, Automation and Test in Europe (DATE), 2010.
[156] B Daniel Große, Görschwin Fey, and Rolf Drechsler. Enhanced formal verification flow for circuits integrating debugging and coverage analysis. In Specification - Transformation - Navigation, Festschrift dedicated to Bernd Krieg-Brückner on Occasion of his 60th Birthday, 2009.
[157] B Daniel Große. Using formal methods for verification of complex systems. In EDAA/DATE PhD Forum at Design, Automation and Test in Europe, 2008.
[158] B Daniel Große, Rolf Drechsler, Vasco Jerinic, Jan Langer, Erhard Fehlauer, Frank Roging, Steffen Rülke, Frank Dresig, Christian Haufe, Thomas Berndt, and Hans-Jürgen Brand. Analysemethoden für unsichere Anwendungsbedingungen - Beiträge von AMD Fraunhofer IIS/EAS, TU Chemnitz und Uni Bremen zu Arbeitspaket 3. In edaWorkshop (Poster), 2008.
[159] B Daniel Große, Vasco Jerinic, Jan Langer, R. Beckert, Erhard Fehlauer, Frank Roging, Steffen Rülke, Hans-Jürgen Brand, Frank Dresig, Christian Haufe, and Thomas Berndt. Analysemethoden für unsichere Anwendungsbedingungen - Beiträge von AMD Fraunhofer IIS/EAS, TU Chemnitz und Uni Bremen zu Arbeitspaket 3. In edaWorkshop (Poster), 2007.
[160] B Daniel Große and Rolf Drechsler. Debugging in der Constraint-gesteuerten Zufallssimulation. In URANOS-Workshop Anwendungsrobuster Entwurf nanoelektronischer Systeme, 2007.
[161] B Daniel Große, Jan Langer, R. Beckert, H. Süße, Erhard Fehlauer, Frank Roging, Frank Dresig, Christian Haufe, and Thomas Berndt. Analysemethoden für unsichere Anwendungsbedingungen. In Ekompass-Workshop (Poster), 2006.
[162] B Daniel Große and Rolf Drechsler. Verifikation mit Constraint-gesteuerter Zufallssimulation. In URANOS-Workshop Anwendungsrobuster Entwurf nanoelektronischer Systeme, 2006.