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JOURNALS


CONFERENCES



» Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods




Author:

Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Reference:

Barcelona, Spain, 2022
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection




Author:

Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference:
40th IEEE VLSI Test Symposium (VTS)
Reference:

San Diego, USA, 2022
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks




Author:

Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference:
34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Reference:

Athens, Greece, 2021
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» ALF – A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks




Author:

Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler
Conference:
The Genetic and Evolutionary Computation Conference (GECCO)
Reference:

Lille, France, 2021
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Machine Learning through Evolving Combined Deep Neural Networks




Author:

Rune Krauss, Marcel Merten, Mirco Bockholt, Saman Fröhlich, Rolf Drechsler
Conference:
Genetic and Evolutionary Computation Conference (GECCO)
Reference:

Electronic-only, 2020
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]


WORKSHOPS




» SAT-based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms




Author:

Marcel Merten, Mohammed E. Djeridane, Sebastian Huhn, Rolf Drechsler
Workshop:
15th International Workshop on Boolean Problems (IWSBP)
Reference:

Bremen, 2022
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods




Author:

Marcel Merten, Sebastian Huhn and Rolf Drechsler
Workshop:
34. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Bremerhaven, Germany, 2022
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» A Codeword-based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks




Author:

Sebastian Huhn, Marcel Merten, Stephan Eggersglüß and Rolf Drechsler
Workshop:
30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Freiburg (Breisgau), Germany, 2018
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]

















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