Only available in German
Digital Systems Modeling using Verilog and SystemVerilog: Design, Test and Synthesis
G | 03-BE-701.07
(in englischer Sprache)
Themen:
- Digital systems design using Verilog
- HDL simulation
- Building robust testbenches using SystemVerilog
- Good practices in Digital systems verification using SVA
- Basic static timing analysis and HW optimization
- Importance of synthesis concept
