The Group of Computer Architecture offer lectures in the area of computer aided design of circuits and systems for students on bachelor- and master-level. Beside the lectures for graduate and undergraduate students, we run student team projects to enforce research oriented learning. In research the groups are successful in Computer Aided Design (CAD) of circuits and systems covering synthesis, verification, test and reliability.
I am the head of the group of computer architecture. The main focus of the group is the development and application of CAD tools in circuit design. The research areas range from system descriptions in SystemC over test and verification down to synthesis. For further information see www.rolfdrechsler.de
Together with Birthe Semken I work as team assistant in the Group for Computer Architecture. I am responsible for all issues concerning the administration of the group. In particular, I administrate the projects funded by third parties.
Together with Regine Janssen I work as team assistant in the Group for Computer Architecture.
I am responsible for all issues concerning the administration of the group. In particular, I plan and process the official journeys of the group members.
Within the Scale4Edge research project I am currently working on methods for verification and validation of embedded systems across layers of abstraction.
A central aspect is the open standard instruction set architecture RISC-V which provides the interface between software and hardware.
I am interested in the verification of complex heterogeneous systems. My current goal is to increase the confidence in high-level verification of SystemC AMS models by showing equivalence between SystemC AMS representations and low-level representations of heterogeneous systems.
The focus of my research lies in the field of natural language processing (NLP). Therefore, artificial intelligence, computational linguistics and machine learning are important aspects of my work. The goal is to fill as many gaps in linguistic research with intelligent systems that can be applied in everyday life.
My research interests include network security and data science. My investigations focus on the applications of machine learning to network traffic data to build models for identifying cyberattacks and abnormal behaviors. Currently, I am working on correlating different security solutions like Security Information and Event Management (SIEM), Cyber Threat Intelligence (CTI), and cybersecurity data analytics to the Security Operations Centers (SOC).
I am concerned with Approximate Computing and Artificial Intelligence (AI). In particular, I am trying to develop methods to incorporate Approximate Computing techniques into AI algorithms such that the benefit from the use of Approximate Computing is maximized. At the same time, it must be ensured that the functionality of the AI is guaranteed.
My research interest is system level design and verification. Currently I am working on SystemC designs visualization for understanding of a given system. The problem is that the extraction of data from system designs written in SystemC is crucial. It brings this challenge that how can both, the structure and the behavior of a given SystemC design be retrieved without restricting the language means and/or modifying the existing infrastructures?
My research mainly aims to the development of solutions to enhance the testability of integrated circuits and to improve the quality of the manufacturing test. In this regard, I am modeling state-of-the-art test access mechanisms on system-level, which allows me to orchestrate formal methods yielding to an optimization of certain characteristics already in an early design phase.
I am interested in the verification of systems on high levels of abstraction.
My current research focus is on fully automatic formal methods for property checking as well as bug hunting in SystemC (TLM) models.
The inherent concurrency of the models in combination with the large input space, requires sophisticated proof techniques.
My activity is focused on the development of algorithms for high-quality test set generation for digital circuits. An important aspect of my work lies in the integration and profitable use of structural knowledge about the design under test within formal proof techniques, which are applied by the test computation process.
My research activity includes real-time data acquisition, data management, and data processing for dynamic processes by applying machine learning techniques in conjunction with formal techniques. In the end, my work aims at automating the entire flow by predicting the most beneficial set of parameters for such a dynamic process in soft real-time.
My research topics are Information- and Network Security. My research focus is
‘Adaptive Network Security Services in virtualized Networks’. I am also active in
the field of Digital Computer Forensics, here especially in the topic of ‘Digital
Forensic Readyness’. I have a professorship at the Norwegian University of
Science and Technology (NTNU) in Network Security.
My research area is the formal verification of systems at high levels of abstraction. Currently the focus is the development of an automated formal verification flow for SystemC TLM designs integrating property checking, debugging, and coverage analysis.
My field of research is formal verification and debugging of gate-level arithmetic circuits specially large and complex multipliers and dividers. These circuits play an important role in different applications, and they usually consist of millions of gates. The idea is to take advantage of fast and scalable methods (e.g. computer algebra) to verify circuits, localize the faults, and make the buggy parts correct.
I am involved in setting up the Data Science Center. The preparation of the data is important for techniques of data science and machine learning. Because of that I deal with the collection, storage, archiving and processing of data. Futher more I am also interested in the areas of distributed and mobile applications as well as infrastructure for high-performance computing.
As part of the Collaborative Research Center EASE I am focusing on formal verification and optimization of plans for autonomous robots. In addition, my interests lie in the areas of automated reasoning and mathematical optimization.
I am working on quantum circuits and reversible logic. My investigations
focus on data structures that allow for the representation of larger
functions in an efficient way and, at the same time, can be used for the
synthesis of corresponding circuits.
As a goal of my research project OptiSecure, I would like to provide security for integrated circuits at the transistor level against non-invasive attacks, in particular optical-probing attacks. Currently, integrated circuits are vulnerable to the optical-probing attack, hence the intellectual properties and information can be hijacked using this technique. As a goal of my research, I would like to design secure circuits and architectures to combat such side-channel attacks. This is an important step to make circuits more secure toward this novel attack.
My main research area is the verification of cryptographic security properties. In researching this topic I combine my interest for cryptology, algebra, number theory, logics and proof techniques, in order to find holistic security proofs that are relevant and applicable in practice.
My research revolves around automated proofing techniques like BDDs and SAT solvers as part of modern verification methods. Currently I am focusing on examining these proofing techniques and optimizing them for verification of complex embedded systems using heuristics at various levels.
In my role as coordinator of the Data Science Center, I support the establishment of interdisciplinary collaborations fostering innovative research approaches related to data science. I am responsible for the management of the Data Science Center as well as its science communication and outreach activities.
The main focus of my research activities is the analysis of description languages for hardware/software design. Major questions are how such hybrid systems can be visualized and what technical prerequisites need to be satisfied for this purpose.
As part of the Scale4Edge research project I am currently working on the verification of embedded systems based on the open standard instruction set architecture RISC-V. The focus of my work lies especially on property checking and program
analysis through symbolic execution techniques.
My research topic is algorithm design for synthesis, optimization, and layout of classical and emerging computer technologies. For this purpose, I apply both heuristic and exact approaches. Besides CMOS, I have experience in the fields of Reversible Logic, Quantum Computing, DNA Computing, and Optical Computing, Digital Microfluidic Biochips (DMFB) as well as Quantum-dot Cellular Automata (QCA) and Nanomagnet Logic (NML).
My main research focus is on reversible logic which shows promising applications e.g. in the area of low-power design and quantum computation. However, till today no design flow for reversible logic exists - this must be changed. In particular, approaches for synthesis, verification, and debugging need improvements. Besides that, I am trying to improve the existing SAT- and SMT-solvers and their application in formal hardware verification.
I am in charge of establishing a graduate school for the high-profile area Minds, Media, Machines. The graduate school aims at connecting existing research training groups, initiate new doctoral programs and promote structured doctoral education in general.
Within the scope of my employment at the Collaborative Research Center 1232, I am developing a framework to process experimental data that are conducted in the field of material science.
As part of this framework, various functionalities are provided concerning the visualization, the qualitative assessment as well as the analysis of correlations of those heterogeneous data sets. I am orchestrating newest web-technologies like Node.js and the document-oriented database system MongoDB to implement these functionalities.