» Polynomial Formal Verification of Floating Point
Adders
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Autor:
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Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler |
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Design, Automation and Test in Europe Conference (DATE) |
Referenz:
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| Antwerp, Belgium, 2023
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Hyperlink:
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| [Link zur Konferenz]
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» Processor Verification using Symbolic Execution: A RISC-V Case-Study
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Autor:
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Niklas Bruns, Vladimir Herdt, Rolf Drechsler |
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Design, Automation and Test in Europe Conference (DATE) |
Referenz:
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| Antwerp, Belgium, 2023
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Hyperlink:
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| [Link zur Konferenz]
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» Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits
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Autor:
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Kemal Çağlar Coşkun, Muhammad Hassan, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Antwerp, Belgium, 2023
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Hyperlink:
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| [Link zur Konferenz]
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» FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing
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Autor:
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Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Antwerp, Belgium, 2023
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Hyperlink:
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| [Link zur Konferenz]
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» Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network
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Autor:
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Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Antwerp, Belgium, 2023
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Hyperlink:
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| [Link zur Konferenz]
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» Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars
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Autor:
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Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler |
| Konferenz: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
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| Tokyo, Japan, 2023
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - a RISC-V Case Study
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Autor:
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Sajjad Parvin, Mehran Goli, Frank Sill Torres, and Rolf Drechsler |
| Konferenz: |
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28th Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
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| Tokyo, Japan, 2023
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» EDDY: A Multi-Core BDD Package With Dynamic Memory Management and Reduced Fragmentation
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Autor:
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Rune Krauss, Mehran Goli, Rolf Drechsler |
| Konferenz: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
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| Tokyo, Japan, 2023
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Hyperlink:
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| [Link zur Konferenz]
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» A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS
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Autor:
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Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große |
| Konferenz: |
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Design and Verification Conference in Europe (DVCon Europe) |
Referenz:
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| Munich, Germany, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Monitoring the Effects of Static Variable Orders on the Construction of BDDs
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Autor:
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Khushboo Qayyum, Alireza Mahzoon, Rolf Drechsler |
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International Interdisciplinary Conference on Mathematics, Engineering and Science (MESIICON) |
Referenz:
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| Virtual Conference, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Polynomial Formal Verification: Ensuring Correctness under Resource Constraints
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Autor:
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Rolf Drechsler, Alireza Mahzoon |
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International Conference on Computer Aided Design (ICCAD) |
Referenz:
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| San Diego, USA, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Divider Verification Using Symbolic Computer Algebra and Delayed Don’t Care Optimization
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Autor:
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Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Formal Methods in Computer-Aided Design (FMCAD) |
Referenz:
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| Trento, Italy, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Preserving Design Hierarchy Information for Polynomial Formal Verification
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Autor:
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Rolf Drechsler, Alireza Mahzoon |
| Konferenz: |
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IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Referenz:
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| Patras, Greece, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications
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Autor:
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Kamalika Datta, Saman Froehlich, Saeideh Shirinzadeh, Dev Narayan, Yadav Indranil Sengupta and Rolf
Drechsler |
| Konferenz: |
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IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Referenz:
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| Patras, Greece, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Fast and Exact is Doable: Polynomial Algorithms in Test and Verification
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Autor:
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Rolf Drechsler |
| Konferenz: |
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IEEE Latin-American Test Symposium (LATS) |
Referenz:
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| Virtual Conference, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Design Modification for Polynomial Formal Verification
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Autor:
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Rolf Drechsler, Alireza Mahzoon
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| Konferenz: |
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2022 International Symposium on Electrical, Electronics and Information Engineering (ISEEIE) |
Referenz:
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| Virtual Conference, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling
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Autor:
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Christopher Metz, Mehran Goli, Rolf Drechsler |
| Konferenz: |
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ACM/IEEE Workshop on Machine Learning for CAD (MLCAD) |
Referenz:
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| Snowbird, USA, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Next Generation Design For Testability, Debug and
Reliability Using Formal Techniques
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Autor:
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Sebastian Huhn and Rolf Drechsler |
| Konferenz: |
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International Test Conference (ITC) |
Referenz:
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| Anaheim, CA, USA, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device
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Autor:
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Alexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler
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| Konferenz: |
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Forum on Specification & Design Languages (FDL) |
Referenz:
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| Linz, Austria, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification
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Autor:
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Niklas Bruns, Vladimir Herdt, Rolf Drechsler
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| Konferenz: |
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Forum on Specification & Design Languages (FDL) |
Referenz:
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| Linz, Austria, 2022
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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