» A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
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Autor:
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Marcel Merten, Sebastian Huhn, Rolf Drechsler |
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34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
Referenz:
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| Athens, Greece, 2021
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Hyperlink:
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| [Link zur Konferenz]
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» Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs
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Autor:
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Mehran Goli, Rolf Drechsler |
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International Conference on Computer Aided Design (ICCAD) |
Referenz:
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| Munich, Germany, 2021
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Hyperlink:
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| [Link zur Konferenz]
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» Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level
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Autor:
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Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler |
| Konferenz: |
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IFIP/IEEE International Conference on
Very Large Scale Integration (VLSI-SoC) |
Referenz:
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| Virtual Conference, Singapore, 2021
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Hyperlink:
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| [Link zur Konferenz]
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» RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems
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Autor:
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Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
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Forum on Specification & Design Languages (FDL) |
Referenz:
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| Antibes, France, 2021
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Hyperlink:
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| [Link zur Konferenz]
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» VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes
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Autor:
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Mehran Goli, Rolf Drechsler |
| Konferenz: |
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Forum on Specification & Design Languages (FDL) |
Referenz:
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| Antibes, France, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes
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Autor:
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Sören Tempel, Vladimir Herdt, Rolf Drechsler |
| Konferenz: |
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Forum on Specification & Design Languages (FDL) |
Referenz:
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| Antibes, France, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Work-in-Progress: Early Power Estimation of CUDA-based CNNs on GPGPUs
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Autor:
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Christopher Metz, Mehran Goli, Rolf Drechsler |
| Konferenz: |
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International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) |
Referenz:
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| VIRTUAL CONFERENCE, 2021
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Hyperlink:
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| [Link zur Konferenz]
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» Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level
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Autor:
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Pascal Pieper, Ralf Wimmer, Gerhard Angst, Rolf Drechsler |
| Konferenz: |
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31st ACM Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
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| Virtual Conference, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Finding Optimal Implementations of Non-native CNOT Gates using SAT
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Autor:
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Philipp Niemann, Luca Müller, Rolf Drechsler |
| Konferenz: |
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Reversible Computation (RC) |
Referenz:
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| Nagoya, Japan, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation
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Autor:
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Philipp Niemann, Luca Müller, Rolf Drechsler |
| Konferenz: |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Palermo, Sicily, Italy, 2021
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Hyperlink:
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| [Link zur Konferenz]
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» Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
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Autor:
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Mehran Goli, Alireza Mahzoon, Rolf Drechsler |
| Konferenz: |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Palermo, Sicily, Italy, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» ALF – A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks
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Autor:
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Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler |
| Konferenz: |
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The Genetic and Evolutionary Computation Conference (GECCO) |
Referenz:
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| Lille, France, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability
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Autor:
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Payam Habiby, Sebastian Huhn, Rolf Drechsler
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| Konferenz: |
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28th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) |
Referenz:
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| Apulia, Italy, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic
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Autor:
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Philipp Niemann, Rolf Drechsler |
| Konferenz: |
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51st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Nursultan, Kazakhstan, 2021
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Hyperlink:
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| [Link zur Konferenz]
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Vortrag:
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| [Link Vortragsvideo]
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PDF:
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| [hier ansehen]
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» Depth Optimized Synthesis of Symmetric Boolean Functions
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Autor:
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Martha Schnieber, Saman Fröhlich, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
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| Tampa, Florida, USA, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Domain-driven correlation-aware recombination and mutation operators for complex real-world applications
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Autor:
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Christina Plump, Bernhard J. Berger, Rolf Drechsler |
| Konferenz: |
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IEEE Congress on Evolutionary Computation (CEC) |
Referenz:
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| Kraków, Poland, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Improving evolutionary algorithms by enhancing an approximative fitness function through prediction intervals
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Autor:
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Christina Plump, Bernhard J. Berger, Rolf Drechsler |
| Konferenz: |
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IEEE Congress on Evolutionary Computation (CEC) |
Referenz:
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| Krakow, Poland, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» PolyAdd: Polynomial Formal Verification of Adder Circuits
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Autor:
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Rolf Drechsler |
| Konferenz: |
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24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| Vienna, Austria, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing
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Autor:
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Sören Tempel, Vladimir Herdt, Rolf Drechsler |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| San Francisco, USA, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Late Breaking Results: Polynomial Formal Verification of Fast Adders
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Autor:
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Alireza Mahzoon, Rolf Drechsler |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| San Francisco, USA, 2021
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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