INHALT & PFAD:
Application of Formal Methods to the Test of Digital Circuits
Uhrzeit: 15.00 Uhr s.t.
Ort: MZH 8090
Vortragende(r): Dr. Matthias Sauer
(Albert ‐ Ludwigs ‐ Universität Freiburg)
Miniaturized electronic devices have changed the habits of people worldwide and led to the development of a connected world with data access everywhere and every time. Such innovations would not be possible without the increased capabilities of current production processes. During the last years, the community has managed to keep the famous Moore's law still in place and succeeded in cutting power consumption while at the same time reducing the size and cost of each transistor. However, these improvements in the production processes also lead to increased challenges connected to the testing of these devices and hence to assess the reliability of such devices in e.g., safety‐critical environments. Current testing processes have reached a point, where classical pass/fail testing methods were replaced by grading based techniques, assessing the quality of a test set not only by its primary testing capability but in addition with regards to secondary objectives e.g., meeting timing constraints or managing the power consumption. Hence, testing of digital circuits evolved from the straightforward problem to generate a test for a given fault to a multi‐constraint optimization problem. As a consequence, the complexity of test generation procedures greatly increased requiring novel and innovative reasoning techniques. Within this talk, such new techniques based on formal methods such as the Boolean satisfiability problem (SAT) and its extensions with a special emphasis of MaxSAT‐based optimization will be presented and their application for several important aspects within the test digital circuits will be discussed.
Dr. Matthias Sauer is a post‐doctoral researcher within the Computer Architecture Group at the University of Freiburg. He studied computer science in Freiburg and received his PhD from the same university in 2013. His research interests include computer‐aided design, test pattern generation for digital circuits and hardware security, with a special focus on the application of formal methods within these fields.
Ansprechpartner(in) / Einladende(r):
Prof. Dr. Rolf