// This is a SyReC-file describing an arithmetic logic unit (including addition, subtraction, multiplication, and division) with a flattened control structure.
// This file has been taken from RevLib (www.revlib.org). 

module alu( in op( 2 ), out x0( 16 ), inout x1( 16 ), inout x2( 16 ) )

if ( op = 0 )  then
  x0 ^ = ( x1 + x2 )
else
  skip
fi ( op = 0 );
if ( op = 1 )  then
  x0 ^ = ( x1 - x2 )
else
  skip
fi ( op = 1 );
if ( op = 2 )  then
  x0 ^ = ( x1 * x2 )
else
  skip
fi ( op = 2 );
if ( op = 3 )  then
  x0 ^ = ( x1 / x2 )
else
  skip
fi ( op = 3 )
