// This is a SyReC-file describing a logic-unit applying bit-wise operations (i.e. bit-wise AND, bit-wise OR, bit-wise XOR).
// This file has been taken from RevLib (www.revlib.org).

module lu( in op(2), out x0, inout x1, inout x2 )

  if ( op = 0 )
    then
      x0 ^ = ( x1 & x2 )
    else
      if ( op = 1 )
        then
          x0 ^ = ( x1 | x2 )
        else
          if ( op = 2 )
            then
              x0 ^ = ( x1 ^ x2 )
            else
              x0 ^ = x1 ;
              ~= x0
          fi ( op = 2 )
      fi ( op = 1 )
  fi ( op = 0 )
