// This is a SyReC-file describing a circuit with a nested control structure.
// This file has been taken from RevLib (www.revlib.org). 

module main( inout x, inout a(1), inout b(1), inout y )
  if ( a || b ) then
    ~= y;
    if ( a > b ) then
      ++= x;
      x ^= y
    else 
      ~= y;
      if ( a && b ) then
        ++= x;
        x ^= y
      else 
        --= x
      fi ( a && b );
      ~=y
    fi ( a > b );
    ~=y
  else
    ~= y;
    if ( a = b ) then
      ++= x;
      x ^= y
    else 
      --= x
    fi ( a = b );
    ~=y
  fi ( a || b )