// This is a SyReC-file describing a circuit with a nested control structure.
// This file has been taken from RevLib (www.revlib.org). 

module main( inout a(1), inout b(1), inout x, inout y )
  if a then
    if b then
      x += y
    else
      y += x
    fi b
  else
    if b then
      x -= y
    else
      y -= x
    fi b
  fi a
