Overview

This page gives an outline of all components in the libraries.

Core

gateGate class
circuitCircuit class new features
functorGeneric Functor Implementation based on Boost.Function.
propertiesProperty Map Implementation for Algorithms new features
target_tagsPredefined target type tags for common gate types new features
truth_tableClass for truth table representation
versionReturns RevKit version new features
Functions
active_controlsSlot for adding control lines automatically new features
add_circuitPrepending, inserting and appending circuits to another circuit
add_gatesAdding typical gates to a circuit new features
add_line_to_circuitAdd a line to a circuit with specifying all meta-data
circuit_hierarchyReturns the hierarchy of a circuits by its modules new features
circuit_to_truth_tableGenerates a truth table from a circuit
clear_circuitClears a circuit
control_linesGets the control lines of a gate
copy_circuitCopies a circuit
copy_metadataCopies meta-data from a specification to a circuit
expand_circuitExpand a circuit on the base of a sub circuit
extend_truth_tableRemoves the Don't Care Values of a binary truth table
find_linesFinds empty and non-empty lines in circuits and gates
flatten_circuitFlattens a circuit with modules new features
fully_specifiedDetermines whether a truth_table is fully specified
reverse_circuitReverse a circuit
target_linesGets the target lines of a gate
I/O
create_imageLaTeX functions for printing circuits
print_circuitConsole output of a circuit new features
print_statisticsPrint statistics about a circuit
read_realizationParser for RevLib realization (*.real) file format
read_specificationParser for RevLib specification (*.spec) file format
read_plaReads a specification from a PLA file
revlib_parserRevLib file format parser new features
revlib_processorProcessor which works with the revlib_parser new features
write_blifWrites a circuit to a BLIF file
write_realizationGenerator for RevLib realization (*.real) format
write_specificationWrites a truth table to a RevLib specification file
write_verilogWrites a circuit to a Verilog file new features
Meta
bus_collectionBus Collection new features
Utils
costsCost calculation for circuits new features
program_optionsEasier access to program options
timerA generic way for measuring time new features

Algorithms

Optimization
adding_linesAdding Lines Optimization new features
line_reductionLine Reduction Optimization new features
window_optimizationWindow Optimization
Synthesis
bdd_synthesisBDD Based Synthesis
embed_truth_tableEmbedding of an irreversible specification
esop_synthesisESOP Based Synthesis
exact_synthesisExact Synthesis of Reversible Networks
kfdd_synthesisKFDD Based Synthesis
quantum_decompositionQuantum Decomposition of Reversible Circuits
swopSWOP - Synthesis With Output Permutation
transformation_based_synthesisTransformation Based Synthesis
Simulation
partial_simulationSimulation considering constant inputs and garbage outputs
simple_simulationVery simple simulation, only efficient for small circuits
Verification
equivalence_checkSAT-based equivalence check (respects garbage outputs and constant inputs)

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