File List

Here is a list of all documented files with brief descriptions:
active_controls.hppSlot for adding control lines automatically
add_circuit.hppPrepending, inserting and appending circuits to another circuit
add_gates.hppAdding typical gates to a circuit
add_line_to_circuit.hppAdd a line to a circuit with specifying all meta-data
adding_lines.hppAdding Lines Optimization
bdd_synthesis.hppBDD Based Synthesis
bus_collection.hppBus Collection
circuit.hppCircuit class
circuit_hierarchy.hppReturns the hierarchy of a circuits by its modules
circuit_to_truth_table.hppGenerates a truth table from a circuit
clear_circuit.hppClears a circuit
control_lines.hppGets the control lines of a gate
copy_circuit.hppCopies a circuit
copy_metadata.hpp
costs.hppCost calculation for circuits
create_image.hppLaTeX functions for printing circuits
create_simulation_pattern.hppCreate simulation pattern for sequential simulation
embed_truth_table.hppEmbedding of an irreversible specification
equivalence_check.hppSAT-based equivalence check (respects garbage outputs and constant inputs)
esop_synthesis.hppESOP Based Synthesis
exact_synthesis.hppExact Synthesis of Reversible Networks
expand_circuit.hppExpand a circuit on the base of a sub circuit
extend_truth_table.hppRemoves the Don't Care Values of a binary truth table
find_lines.hppFinds empty and non-empty lines in circuits and gates
flatten_circuit.hppFlattens a circuit with modules
fully_specified.hppDetermines whether a truth_table is fully specified
functor.hppGeneric Functor Implementation based on Boost.Function
gate.hppGate class
kfdd_synthesis.hppKFDD Based Synthesis
line_reduction.hppLine Reduction Optimization
optimization.hppGeneral Optimization type definitions
partial_simulation.hppSimulation considering constant inputs and garbage outputs
pattern.hppData Structure for Simulation Pattern
print_circuit.hppConsole output of a circuit
print_statistics.hppPrint statistics about a circuit
program_options.hppEasier access to program options
properties.hppProperty Map Implementation for Algorithms
quantum_decomposition.hppQuantum Decomposition of Reversible Circuits
read_pattern.hppParser for Simulation pattern
read_pla.hppReads a specification from a PLA file
read_realization.hppParser for RevLib realization (*.real) file format
read_specification.hppParser for RevLib specification (*.spec) file format
reverse_circuit.hppReverse a circuit
revlib_parser.hppRevLib file format parser
revlib_processor.hppProcessor which works with the revlib_parser
sequential_simulation.hppSequential Simulation considering state inputs
simple_simulation.hppVery simple simulation, only efficient for small circuits
simulation.hppGeneral Simulation type definitions
swop.hppSWOP - Synthesis With Output Permutation
synthesis.hppGeneral Synthesis type definitions
target_lines.hppGets the target lines of a gate
target_tags.hppPredefined target type tags for common gate types
timer.hppA generic way for measuring time
transformation_based_synthesis.hppTransformation Based Synthesis
truth_table.hppClass for truth table representation
verification.hppGeneral Verification type definitions
version.hppReturns RevKit version
window_optimization.hppWindow Optimization
write_blif.hppWrites a circuit to a BLIF file
write_realization.hppGenerator for RevLib realization (*.real) format
write_specification.hppWrites a truth table to a RevLib specification file
write_verilog.hppWrites a circuit to a Verilog file
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