Space-Efficient FPGA-Accelerated Collision Detection for Virtual Prototyping
We present a space-efficient,
FPGA-optimized architecture to detect collisions among virtual objects,
as well as simulation results for collision queries using this architecture.
The design consists of two main modules, one for traversing a hierarchical
acceleration data structure, and one for intersecting triangles.
This paper focuses on the former.
is based on a novel algorithm for testing discretely oriented polytopes for
overlap in 3D space. In addition, we derive a new overlap test algorithm that
can be implemented using fixed-point arithmetic without producing false
negatives and with bounded error.
SystemC simulation results on different levels of
abstraction show that real-time collision detection
of complex objects at rates required by force-feedback and
physically-based simulations can be obtained. In addition, synthesis results show
that the design can still be fitted into a six-million gates FPGA.
Furthermore, we compare our FPGA-based design with a fully parallelized
ASIC-targeted architecture and a software implementation.
author = "Andreas Raabe and Stefan Hochgürtel and
Gabriel Zachmann and Joachim K.~Anlauf",
title = "Space-Efficient FPGA-Accelerated Collision Detection for
booktitle = "Design Automation and Test in Europe (DATE)",
year = "2006",
month = mar # "6--10",
address = "Munich, Germany",
url = "http://www.collisionchip.de",
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