Universität Bremen  
  Universität Bremen FB3 TZI BISS  
  AG BS > Embedded Systems Testing Benchmarks Site > > Deutsch

Ceiling Speed Monitoring Rev. 1.6


The ceiling speed monitoring model is a functionality of the European Vital Computer EVC, the on board controller that is described in the public European Train Control System ETCS specification.
The model exists as an Enterprise Architect model, a Eclipse/Papyrus model and as an Artisan Studio model. All models contain the same requirements definitions, but the requirements tracing information is defined in the Artisan Studio and the Papyrus model only. All models define the same behaviour.

Contributors. Jan Peleska, Cecile Braunstein, Uwe Schulze, Felix Hübner, Wen-ling Huang (University of Bremen, {jp,cecile,uschulze,felixh,huang}@informatik.uni-bremen.de);
Anne E. Haxthausen, Linh Vu Hong (DTU Compute Technical University of Denmark,{aeha,lvho}@dtu.dk)

The work of Cecile Braunstein is funded by ITEA2 project openETCS under grant agreement 11025.
The work of Uwe Schulze and Wen-ling Huang is funded by the EU FP7 COMPASS project under grant agreement no.287829.
The work of Linh Vu Hong is funded by the RobustRailS project funded by the Danish Council for Strategic Research.
Author: uschulze
  AG BS 
Last updated: October 16, 2015   Impressum