AMBITIOUS AND AGILE - Institutional Strategy for Advancing Research Strengths at a Mid-sized University
Publications
2019| • | Mehran Goli, Muhammad Hassan, Daniel Große, and Rolf Drechsler. Security validation of VP-based SoCs using dynamic information flow tracking. it-Information Technology, 61(1):45-58, 2019. |
| • | Mehran Goli, Muhammad Hassan, Daniel Große, and Rolf Drechsler. Automated analysis of virtual prototypes at electronic system level. In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 307-310, 2019. |
| • | Mehran Goli and Rolf Drechsler. Scalable simulation-based verification of systemc-based virtual prototypes. In EUROMICRO Digital System Design Conference (DSD), 2019. |
| • | Sebastian Huhn, Daniel Tille, and Rolf Drechsler. Hybrid architecture for embedded test compression to process rejected test patterns. In 24th IEEE European Test Symposium (ETS), pages 1-2, 2019. |
| • | Sebastian Huhn, Daniel Tille, and Rolf Drechsler. A hybrid embedded multichannel test compression architecture for low-pin count test environments in safety-critical systems. In 3rd Internation Test Conference in Asia (ITC-Asia), pages 1-6, 2019. |
| • | Sebastian Huhn, Stefan Frehse, Robert Will, and Rolf Drechsler. Determing application-specific knowledge for improving robustness of sequential circuits. In IEEE Transactions On Very Large Scale Integration (VLSI) Systems, pages 875-887, 2019. |
| • | Sebastian Huhn, Stephan Eggersglüß, and Rolf Drechsler. Enhanced embedded test compression technique for processing incompressible test patterns. In 31. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ), 2019. |
| • | Tom L. Koller, Tim Laue, and Udo Frese. State observability through prior knowledge a conceptional paradigm in inertial sensing. In Proceedings of the 16th International Conference on Informatics in Control, Automation and Robotics (ICINCO), 2019. (accepted). |
| • | Alireza Mahzoon, Daniel Große, and Rolf Drechsler. GenMul: Generating architecturally complex multipliers to challenge formal verification tools. In International Workshop on Logic Synthesis (IWLS), 2019. |
| • | Alireza Mahzoon, Daniel Große, and Rolf Drechsler. RevSCA: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers. In Design Automation Conference (DAC), pages 185:1-185:6, 2019. |
| • | Rehab Massoud, Hoang M. Le, and Rolf Drechsler. Property-driven timestamps encoding for timeprints-based tracing and monitoring. In International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS), 2019. |
| • | Rehab Massoud, Hoang M. Le, Peter Chini, Prakash Saivasan, Roland Meyer, and Rolf Drechsler. Temporal tracing of on-chip signals using timeprints. In Design Automation Conference (DAC), pages 186:1-186:6, 2019. |
| • | Saeideh Shirinzadeh and Rolf Drechsler. In-memory computing: The integration of storage and processing. In Cornelia S. Große and Rolf Drechsler, editors, Information Storage A Multidisciplinary Perspective. Springer, 2019. |
| • | Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Combining sequentialization-based verification of multi-threaded C programs with symbolic partial order reduction. Software Tools for Technology Transfer (STTT), 2019. |
| • | Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, and Rolf Drechsler. Placement & routing for tile-based field-coupled nanocomputing circuits is NP-complete. Journal on Emerging Technologies in Computing Systems (JETC), 2019. |
| • | Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Towards formal verification of plans for cognition-enabled autonomous robotic agents. In EUROMICRO Symposium on Digital System Design (DSD), 2019. |
| • | Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, and Rolf Drechsler. SAT-Hard: A learning-based hardware SAT-solver. In EUROMICRO Symposium on Digital System Design (DSD), 2019. |
| • | Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, and Rolf Drechsler. Ignore clocking constraints: An alternative physical design methodology for field-coupled nanotechnologies. In IEEE Annual Symposium on VLSI (ISVLSI), 2019. |
| • | Vladimir Herdt, Daniel Große, Hoang M. Le, and Rolf Drechsler. Early concolic testing of embedded binaries with virtual prototypes: A RISC-V case study. In Design Automation Conference (DAC), pages 188:1-188:6, 2019. |
| • | Kenneth Schmitz, Buse Ustaoglu, Daniel Große, and Rolf Drechsler. (ReCo)Fuse your PRC or lose security: Finally reliable reconfiguration-based countermeasures on FPGAs. In International Symposium on Applied Reconfigurable Computing (ARC), pages 112-126, 2019. |
| • | Hoang M. Le, Daniel Große, Niklas Bruns, and Rolf Drechsler. Detection of hardware trojans in SystemC HLS designs via coverage-guided fuzzing. In Design, Automation and Test in Europe (DATE), pages 602-605, 2019. |
| • | Muhammad Hassan, Daniel Große, Hoang M. Le, and Rolf Drechsler. Data flow testing for SystemC-AMS timed data flow models. In Design, Automation and Test in Europe (DATE), pages 366-371, 2019. |
| • | Vladimir Herdt, Daniel Große, Hoang M. Le, and Rolf Drechsler. Verifying instruction set simulators using coverage-guided fuzzing. In Design, Automation and Test in Europe (DATE), pages 360-365, 2019. |
| • | Saman Froehlich, Daniel Große, and Rolf Drechsler. One method - all error-metrics: A three-stage approach for error-metric evaluation in approximate computing. In Design, Automation and Test in Europe (DATE), pages 284-287, 2019. |
| • | Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Maximizing power state cross coverage in firmware-based power management. In ASP Design Automation Conf. (ASP-DAC), pages 335-340, 2019. |
| • | Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, and Rolf Drechsler. Scalable design for field-coupled nanocomputing circuits. In ASP Design Automation Conf. (ASP-DAC), pages 197-202, 2019. |
2018
| • | Anika Behrens. What are security patterns?: A formal model for security and design of software. In Proceedings of the 13th International Conference on Availability, Reliability and Security (ARES), pages 35:1-35:6, 2018. |
| • | Mehran Goli, Jannis Stoppe, and Rolf Drechsler. Resilience evaluation for approximating systemc designs using machine learning techniques. In IEEE International Symposium on Rapid System Prototyping (RSP), pages 97-103, 2018. |
| • | Mehran Goli, Jannis Stoppe, and Rolf Drechsler. Automated non-intrusive analysis of electronic system level designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pages 1-1, 2018. |
| • | Sebastian Huhn, Marcel Merten, Stephan Eggersglüß, and Rolf Drechsler. A codeword-based compaction technique for on-chip generated debug data using two-stage artificial neural networks. In 30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ), 2018. |
| • | Jannis Ulrich Stoppe, Christina Plump, Sebastian Huhn, and Rolf Drechsler. Building fast multi-agent systems using hardware design languages for high-throughput systems. In 6th International Conference on Dynamics in Logistics (LDIC), pages 400-405, 2018. |
| • | Buse Ustaoglu, Sebastian Huhn, Daniel Große, and Rolf Drechsler. SAT-Lancer: a hardware SAT-solver for self-verification. In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 479-482, 2018. |
| • | David Lemma, Daniel Große, and Rolf Drechsler. Natural language based power domain partitioning. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 101-106, 2018. |
| • | David Lemma, Mehran Goli, Daniel Große, and Rolf Drechsler. Power intent from initial ESL prototypes: Extracting power management parameters. In Nordic Circuits and Systems Conference (NORCAS), pages 1-6, 2018. |
| • | Alireza Mahzoon, Daniel Große, and Rolf Drechsler. PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. In International Conference on Computer-Aided Design (ICCAD), pages 129:1-129:8, 2018. (Best Paper Award). |
| • | Alireza Mahzoon, Daniel Große, and Rolf Drechsler. Combining symbolic computer algebra and boolean satisfiability for automatic debugging and fixing of complex multipliers. In IEEE Annual Symposium on VLSI (ISVLSI), pages 351-356, 2018. |
| • | Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto García Ortiz, and Rolf Drechsler. Reliability improvements for multiprocessor systems by health-aware task scheduling. In 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), pages 247-250, 2018. |
| • | Rehab Massoud, Jannis Stoppe, Karthik Maddikunta, and Rolf Drechsler. Time-stamps for hardware simulation models accurate time-back annotation. In 5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe), 2018. |
| • | Saeideh Shirinzadeh and Rolf Drechsler. Logic synthesis for in-memory computing using resistive memories. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 375-380, 2018. |
| • | Saeideh Shirinzadeh, Kamalika Datta, and Rolf Drechsler. Logic design using memristors: An emerging technology. In IEEE International Symposium on Multiple-Valued Logic (ISMVL), pages 121-126, 2018. |
| • | Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, and Rolf Drechsler. Logic synthesis for RRAM-based in-memory computing. IEEE Trans. on CAD of Integrated Circuits and Systems, 37(7):1422-1435, 2018. |
| • | Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Verifying SystemC using intermediate verification language and stateful symbolic simulation. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), 2018. |
| • | Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, and Rolf Drechsler. Behaviour driven development for hardware design. IPSJ Transactions on System LSI Design Methodology, 2018. |
| • | Thilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große. Using constraints for SystemC AMS design and verification. In Design and Verification Conference and Exhibition Europe (DVCon Europe), 2018. |
| • | Vladimir Herdt, Daniel Große, Hoang M. Le, and Rolf Drechsler. Extensible and configurable RISC-V based virtual prototype. In Forum on Specification and Design Languages (FDL), 2018. |
| • | Saman Froehlich, Daniel Große, and Rolf Drechsler. Towards reversed approximate hardware design. In EUROMICRO Symposium on Digital System Design (DSD), 2018. |
| • | Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, and Rolf Drechsler. Evaluating the impact of interconnections in quantum-dot cellular automata. In EUROMICRO Symposium on Digital System Design (DSD), 2018. |
| • | Frank Sill Torres, Marcel Walter, Robert Wille, Daniel Große, and Rolf Drechsler. Synchronization of clocked field-coupled circuits. In International Conference on Nanotechnology (NANO), 2018. |
| • | Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, and Rolf Drechsler. Towards dynamic execution environment for system security protection against hardware flaws. In IEEE Annual Symposium on VLSI (ISVLSI), pages 557-562, 2018. |
| • | Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, and Rolf Drechsler. Testbench qualification for SystemC-AMS timed data flow models. In Design, Automation and Test in Europe (DATE), pages 857-860, 2018. |
| • | Saman Froehlich, Daniel Große, and Rolf Drechsler. Approximate hardware generation using symbolic computer algebra employing Gröbner basis. In Design, Automation and Test in Europe (DATE), pages 889-892, 2018. |
| • | Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, and Rolf Drechsler. An exact method for design exploration of Quantum-dot Cellular Automata. In Design, Automation and Test in Europe (DATE), pages 503-508, 2018. |
| • | Hoang M. Le, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Resiliency evaluation via symbolic fault injection on intermediate code. In Design, Automation and Test in Europe (DATE), pages 845-850, 2018. |
| • | Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards fully automated TLM-to-RTL property refinement. In Design, Automation and Test in Europe (DATE), pages 1508-1511, 2018. |
| • | Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, and Rolf Drechsler. Approximation-aware testing for approximate circuits. In ASP Design Automation Conf. (ASP-DAC), pages 239-244, 2018. |
2017
| • | Gökçe Aydos and Görschwin Fey. Empirical results on parity-based soft error detection with software-based retry. Microprocessors and Microsystems (MICPRO), 48:62-68, 2017. |
| • | Mehran Goli, Jannis Stoppe, and Rolf Drechsler. Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. In Design, Automation and Test in Europe (DATE), pages 630-633, 2017. |
| • | Mehran Goli, Jannis Stoppe, and Rolf Drechsler. Automatic protocol compliance checking of SystemC TLM-2.0 simulation behavior using timed automata. In IEEE International Conference on Computer Design (ICCD), pages 377-384, 2017. |
| • | Tino Flenker and Görschwin Fey. Mapping abstract and concrete hardware models for design understanding. In Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 20-25, 2017. |
| • | Tino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, and Matteo Sonza Reorda. Towards making fault injection on abstract models a more accurate tool for predicting RT-level effects. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 533-538, 2017. |
| • | Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, and Rolf Drechsler. Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. In IEEE Design, Automation and Test in Europe (DATE), pages 578-583, 2017. |
| • | Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, and Lutz Mädler. Exploring superior structural materials using multi-objective optimization and formal techniques. In 6th IEEE International Symposium on Embedded Computing & System Design (ISED), pages 13-17, 2017. |
| • | Sebastian Huhn, Stephan Eggersglüß, and Rolf Drechsler. Reconfigurable TAP controllers with embedded compression for large test data volume. In IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pages 1-6, 2017. |
| • | Sebastian Huhn, Stefan Frehse, Robert Wille, and Rolf Drechsler. Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. In 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pages 182-187, 2017. |
| • | Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, and Rolf Drechsler. Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. In 10th IEEE Symposium Series on Computational Intelligence (SSCI), pages 1-6, 2017. |
| • | Pablo Gonz'alez de Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, and Pablo S'anchez Espeso. Towards a verification flow across abstraction levels verifying implementations against their formal specification. IEEE Trans. on CAD of Integrated Circuits and Systems, 36(3):475-488, 2017. |
| • | Rehab Massoud, Jannis Stoppe, Daniel Große, and Rolf Drechsler. Semi-formal cycle-accurate temporal execution traces reconstruction. In International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS), pages 335-351, 2017. |
| • | Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, and Rolf Drechsler. Endurance management for resistive logic-in-memory computing architectures. In Design, Automation and Test in Europe (DATE), pages 1092-1097, 2017. |
| • | Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, and Rolf Drechsler. An adaptive prioritized ph(ε)-preferred evolutionary algorithm for approximate BDD optimization. In Genetic and Evolutionary Computation Conference (GECCO), pages 1232-1239, 2017. |
| • | Rolf Drechsler and Daniel Große. Verifying next generation electronic systems. In International Conference on Infocom Technologies and Unmanned Systems (ICTUS), pages 6-10, 2017. |
| • | Arun Chandrasekharan, Daniel Große, and Rolf Drechsler. Yise - a novel framework for boolean networks using Y-inverter graphs. In ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), 2017. |
| • | Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. In Forum on Specification and Design Languages (FDL), 2017. |
| • | Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Early SoC security validation by VP-based static information flow analysis. In International Conference on Computer-Aided Design (ICCAD), 2017. |
| • | Arun Chandrasekharan, Daniel Große, and Rolf Drechsler. ProACt: a processor for high performance on-demand approximate computing. In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 463-466, 2017. |
| • | Saman Fröhlich, Daniel Große, and Rolf Drechsler. Error bounded exact BDD minimization in approximate computing. In International Symposium on Multi-Valued Logic (ISMVL), pages 254-259, 2017. |
| • | Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, and Rolf Drechsler. Data flow testing for virtual prototypes. In Design, Automation and Test in Europe (DATE), pages 380-385, 2017. |
| • | Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, and Rolf Drechsler. Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. In ASP Design Automation Conf. (ASP-DAC), pages 57-62, 2017. |
2016
| • | Gökçe Aydos and Görschwin Fey. Exploiting error detection latency for parity-based soft error detection. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 3-8, 2016. |
| • | Mehran Goli, Jannis Stoppe, and Rolf Drechsler. AIBA: an automated intra-cycle behavioral analysis for SystemC-based design exploration. In IEEE International Conference on Computer Design (ICCD), pages 360-363, 2016. |
| • | Tino Flenker and Görschwin Fey. Matching abstract and concrete hardware models for design understanding. In Design Automation for Understanding Hardware Designs (DUHDe), 2016. |
| • | Malgorzata Goldhoorn and Ronny Hartanto. Enhancing Object Detection by using Probabilistic Spatial-Semantic Knowledge. Journal of Computers, 12(01), 2016. |
| • | Sebastian Huhn, Stephan Eggersglüß, and Rolf Drechsler. VecTHOR: Low-cost compression architecture for IEEE-1149.1-compliant TAP controllers. In 21st IEEE European Test Symposium (ETS), pages 1-6, 2016. |
| • | Sebastian Huhn, Stephan Eggersglüß, and Rolf Drechsler. Leichtgewichtige Datenkompressions-Architektur für IEEE-1149.1-kompatible Testschnittstellen. In 28. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ), 2016. |
| • | Jan Peleska, Wen-ling Huang, and Felix Hübner. A Novel Approach to HW/SW Integration Testing of Route-Based Interlocking System Controllers. In Thierry Lecomte, Ralf Pinger, and Alexander Romanovsky, editors, Reliability, Safety, and Security of Railway Systems. Modelling, Analysis, Verification, and Certification, number 9707 in Lecture Notes in Computer Science, pages 32-49. Springer International Publishing, June 2016. |
| • | Judith Peters, Nils Przigoda, Robert Wille, and Rolf Drechsler. Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models. In International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 78-84, 2016. |
| • | Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, and Rolf Drechsler. Frame conditions in symbolic representations of UML/OCL models. In International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 65-70, 2016. |
| • | Nils Przigoda, Mathias Soeken, Robert Wille, and Rolf Drechsler. Verifying the structure and behavior in UML/OCL models using satisfiability solvers. IET Cyper-Phys. Syst.: Theory & Appl., 1(1):49-59, 2016. |
| • | Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, and Rolf Gogolla, Martin Drechsler. Integrating an SMT-based Model Finder into USE. In Workshop on Model-Driven Engineering, Verification and Validation, pages 40-45, 2016. |
| • | Nils Przigoda, Robert Wille, and Rolf Drechsler. Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding. In International Conference on Model Driven Engineering Languages and Systems (MoDELS), 2016. |
| • | Nils Przigoda, Gerhard Dueck, Robert Wille, and Rolf Drechsler. Fault Detection in Parity Preserving Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), pages 44-49, 2016. |
| • | Dennis Schüthe, Felix Wenk, and Udo Frese. Dynamics calibration of a redundant flexible joint robot based on gyroscopes and encoders. In ICINCO 2016 - 13th International Conference on Informatics in Control, Automation and Robotics, 2016. (best paper candidate). |
| • | Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, and Rolf Drechsler. Approximate BDD optimization with prioritized ε-preferred evolutionary algorithm. In Genetic and Evolutionary Computation Conference (GECCO), pages 79-80, 2016. |
| • | Saeideh Shirinzadeh, Mathias Soeken, and Rolf Drechsler. Multi-objective BDD optimization for RRAM based circuit design. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 46-51, 2016. |
| • | Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amaru, Rolf Drechsler, and Giovanni De Micheli. An MIG-based compiler for programmable logic-in-memory architectures. In Design Automation Conference (DAC), pages 117:1-117:6, 2016. |
| • | Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, and Rolf Drechsler. Fast logic synthesis for rram-based in-memory computing using majority-inverter graphs. In Design, Automation and Test in Europe (DATE), pages 948-953, 2016. |
| • | Niels Thole, Lorena Anghel, and Görschwin Fey. A hybrid algorithm to conservatively check the robustness of circuits. In Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2016. |
| • | Amr Sayed Ahmed, Daniel Große, Mathias Soeken, and Rolf Drechsler. Equivalence checking using Gröbner bases. In Int'l Conf. on Formal Methods in CAD (FMCAD), pages 169-176, 2016. |
| • | Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. In Forum on Specification and Design Languages (FDL), pages 1-8, 2016. |
| • | Daniel Große, Hoang M. Le, Muhammad Hassan, and Rolf Drechsler. Guided lightweight software test qualification for IP integration using virtual prototypes. In Int'l Conf. on Comp. Design (ICCD), pages 606-613, 2016. |
| • | Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Compiled symbolic simulation for SystemC. In International Conference on Computer-Aided Design (ICCAD), pages 52:1-52:8, 2016. |
| • | Arun Chandrasekharan, Mathias Soeken, Daniel Große, and Rolf Drechsler. Approximation-aware rewriting of AIGs for error tolerant applications. In International Conference on Computer-Aided Design (ICCAD), pages 83:1-83:8, 2016. |
| • | Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. ParCoSS: efficient parallelized compiled symbolic simulation. In Computer Aided Verification (CAV), pages 177-183, 2016. |
| • | Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, and Görschwin Fey. metaSMT: Focus on your application not on solver integration. Software Tools for Technology Transfer (STTT), pages 1-17, 2016. |
| • | Arun Chandrasekharan, Mathias Soeken, Daniel Große, and Rolf Drechsler. Precise error determination of approximated components in sequential circuits with model checking. In Design Automation Conference (DAC), pages 129:1-129:6, 2016. |
| • | Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, and Rolf Drechsler. Formal verification of integer multipliers by combining Gröbner basis with logic reduction. In Design, Automation and Test in Europe (DATE), pages 1048-1053, 2016. (Best paper candidate). |
| • | Hoang M. Le, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Towards formal verification of real-world SystemC TLM peripheral models - a case study. In Design, Automation and Test in Europe (DATE), pages 1160-1163, 2016. |
| • | Arun Chandrasekharan, Daniel Große, Mathias Soeken, and Rolf Drechsler. Symbolic error metric determination for approximate computing. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 75-76, 2016. |
| • | Mathias Soeken, Daniel Große, Arun Chandrasekharan, and Rolf Drechsler. BDD minimization for approximate computing. In ASP Design Automation Conf. (ASP-DAC), pages 474-479, 2016. |
2015
| • | Gökçe Aydos and Görschwin Fey. Parity-based soft error detection with software-based retry vs. triplication-based soft error correction - an analytical comparison on a flash-based FPGA architecture. In Douglas Cunningham, Petra Hofstedt, Klaus Meer, and Ingo Schmitt, editors, INFORMATIK 2015, volume P-246 of Lecture Notes in Informatics (LNI), pages 1415-1429. Gesellschaft für Informatik, 2015. |
| • | Gökçe Aydos and Görschwin Fey. Empirical results on parity-based soft error detection with software-based retry. In Nordic Circuits and Systems Conference (NORCAS), Oct 2015. |
| • | Gökçe Aydos and Görschwin Fey. In-circuit error detection with software-based error correction - an alternative to TMR. In SyDe Summer School, pages 272-274. Springer, 2015. |
| • | Tino Flenker, André Sülflow, and Görschwin Fey. Diagnostic tests and diagnosis for delay faults using path segmentation. In Asian Test Symposium (ATS), pages 145-150, 2015. |
| • | Malgorzata Goldhoorn and Frank Kirchner. Semantic object recognition based on qualitative probabilistic spatial relations. In Formal Modeling and Verification of Cyber-Physical Systems, pages 278-280. Springer, 2015. |
| • | Matthias Goldhoorn and Frank Kirchner. Constraint-based handling of component networks. In Formal Modeling and Verification of Cyber-Physical Systems, pages 281-283. Springer, 2015. |
| • | Christoph Hilken, Jan Peleska, and Robert Wille. A unified formulation of behavioral semantics for SysML models. In International Conference on Model-Driven Engineering and Software Development, 2015. |
| • | Christoph Hilken and Jan Peleska. Model-based testing against complex sysml models. In SyDe Summer School, pages 284-286. Springer, 2015. |
| • | Felix Hübner and Jan Peleska. Integrated model-based testing and model checking with the benefits of equivalence partition testing. In Formal Modeling and Verification of Cyber-Physical Systems, pages 287-289. Springer, 2015. |
| • | Felix Hübner, Wen-ling Huang, and Jan Peleska. Experimental Evaluation of a Novel Equivalence Class Partition Testing Strategy. In Jasmin Christian Blanchette and Nikolai Kosmatov, editors, Tests and Proofs, number 9154 in Lecture Notes in Computer Science, pages 155-172. Springer International Publishing, July 2015. |
| • | Nils Przigoda, Robert Wille, and Rolf Drechsler. Analyzing Inconsistencies in UML/OCL Models. Journal of Circuits, Systems and Computers, 25(03):1-21, 2015. |
| • | Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, and Rolf Drechsler. Checking Concurrent Behavior in UML/OCL Models. In International Conference on Model Driven Engineering Languages and Systems (MoDELS), pages 176-185, 2015. |
| • | Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, and Rolf Drechsler. Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. In Workshop on Model-Driven Engineering, Verification and Validation, volume 1514 of CEUR Workshop Proceedings, pages 44-47, 2015. |
| • | Nils Przigoda, Robert Wille, and Rolf Drechsler. Leveraging the Analysis for Invariant Independence in Formal System Models. In Euromicro Conference on Digital System Design (DSD), pages 359-366, 2015. |
| • | Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, and Rolf Drechsler. Verification-driven Design Across Abstraction Levels - A Case Study. In Euromicro Conference on Digital System Design (DSD), pages 375-382, 2015. |
| • | Nils Przigoda, Robert Wille, and Rolf Drechsler. Contradiction Analysis For Inconsistent UML/OCL Models. In International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pages 1-6, 2015. |
| • | Nils Przigoda, Robert Wille, and Rolf Drechsler. Verbesserung der fehlersuche in inkonsistenten formalen modellen. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 165-172, 2015. |
| • | Dennis Schüthe and Udo Frese. Optimal control with state and command limits for a simulated ball batting task. In 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), IEEE, pages 3988-3994, 2015. |
| • | Dennis Schüthe. Dynamic rebound control and human robot interaction of a ball playing robot. In Formal Modeling and Verification of Cyber-Physical Systems, volume 1, pages 299-301. Springer Vieweg, 2015. |
| • | Niels Thole and Görschwin Fey. Formal verification of robustness. In Formal Modeling and Verification of Cyber-Physical Systems, pages 305-307. Springer, 2015. |
| • | Niels Thole, Görschwin Fey, and Alberto Garcia-Ortiz. Conservatively analyzing transient faults. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2015. |
| • | Niels Thole, Heinz Riener, and Görschwin Fey. Equivalence checking on system level using a priori knowledge. In Proceedings of the IEEE International Symposium on Design and Diagnostics of Electronic Circuits Systems, pages 177-182, April 2015. |
| • | Niels Thole, Görschwin Fey, and Alberto Garcia-Ortiz. Analyzing an set at gate level using a conservative approach. In Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2015. |
| • | Felix Wenk and Udo Frese. Pose and posture estimation using inertial sensor data. In Formal Modeling and Verification of Cyber-Physical Systems, pages 308-310. Springer, 2015. |
| • | Felix Wenk and Udo Frese. Posture from motion. In Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS 2015), pages 280-285, 2015. |
| • | Mehdi Dehbashi and Görschwin Fey. Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocessors and Microsystems (MICPRO), 39(3):157-166, 2015. |
| • | Melanie Diepenbeck. Completing Behaviour Driven Development for Testing and Verification. PhD thesis, University of Bremen, 2015. |
| • | Judith Peters. Exploiting MARTE/CCSL in Modern Design Flows. PhD thesis, University of Bremen, 2015. |
| • | Judith Peters and Rolf Drechsler. Analyzing and simulating time descriptions from UML/MARTE CCSL. In Formal Modeling and Verification of Cyber-Physical Systems, pages 293-295. Springer, 2015. |
| • | Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, and Rolf Drechsler. A Generic Representation of CCSL Time Constraints for UML/MARTE Models. In The 52st Annual Design Automation Conference 2015, DAC '15, San Francisco, CA, USA, June 7-11, 2015, pages 122:1-122:6, 2015. |
| • | Julia Seiter and Rolf Drechsler. Development of consistent formal models. In Formal Modeling and Verification of Cyber-Physical Systems, 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015, pages 302-304, 2015. |
| • | Julia Seiter. Formal Model Refinement. From Specification to Implementation. PhD thesis, University of Bremen, 2015. |
| • | Eleonora Schönborn, Robert Wille, and Rolf Drechsler. Quo Vadis, Reversible Circuit Design? Towards Scaling Design and Synthesis of Reversible Circuits. In Reed-Muller 2015 Workshop, Waterloo, Canada, May 18-20, 2015. |
| • | Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, and Rolf Drechsler. BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits. In 28th International Conference on VLSI Design, VLSID 2015, Bengaluru, India, January 3-7, 2015, pages 435-440. IEEE, 2015. |
| • | Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, and Rolf Drechsler. Recurrence relations revisited: Scalable verification of bit level multiplier circuits. In IEEE Annual Symposium on VLSI (ISVLSI), pages 1-6, 2015. |
| • | Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, and Rolf Drechsler. Ensuring safety and reliability of ip-based system design - a container approach. In IEEE International Symposium on Rapid System Protoyping (RSP), 2015. |
2014
| • | Malgorzata Goldhoorn and Ronny Hartanto. Semantic Perception using Spatial Potential Fields. In In The 9th International Workshop on Cognitive Robotics (CogRob-2014) of the 21st European Conference on Artificial Intelligence (ECAI-2014), Prague, Czech Republic, 18-22 August, 2014, 2014. |
| • | Malgorzata Goldhoorn and Ronny Hartanto. Semantic labelling of 3D point clouds using spatial object constraints. In In Special Session on Active Robot Vision (WARV 2014) of the 9th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP-2014), Lisbon, Portugal, 05-09 January, 2014. IEEE Computer Society, 2014. |
| • | Matthias Goldhoorn and Sylvain Joyeux. Extension of a plan-based component manager for real time adaptation. In ISR/Robotik 2014; 41st International Symposium on Robotics; Proceedings of, pages 1-6. VDE, 2014. |
| • | Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, and Rolf Drechsler. Verifying consistency between activity diagrams and their corresponding ocl contracts. In Forum on specification & Design Languages (FDL), 2014. |
| • | Cécile Braunstein, Anne E. Haxthausen, Wen-ling Huang, Felix Hübner, Jan Peleska, Uwe Schulze, and Linh Vu Hong. Complete Model-Based Equivalence Class Testing for the ETCS Ceiling Speed Monitor. In Stephan Merz and Jun Pang, editors, Formal Methods and Software Engineering, number 8829 in Lecture Notes in Computer Science, pages 380-395. Springer International Publishing, January 2014. |
| • | Dennis Schüthe and Udo Frese. Task level optimal control of a simulated ball batting robot. In Joaquim Filipe, Oleg Gusikhin, Kurosh Madani, and Jurek Sasiadek, editors, ICINCO 2014 - 11th International Conference on Informatics in Control, Automation and Robotics, volume 2, pages 45-56. SCITEPRESS, 2014. |
| • | Niels Thole and Görschwin Fey. Equivalence checking on system level using stepwise induction. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pages 197-200, 2014. |
| • | Mehdi Dehbashi and Görschwin Fey. Debug Automation from Pre-Silicon to Post-Silicon. Springer, 2015. |
| • | Mehdi Dehbashi and Görschwin Fey. Debug automation for synchronization bugs at RTL. In VLSI Design Conference, pages 44-49, 2014. |
| • | Mehdi Dehbashi and Görschwin Fey. Transaction-based online debug for NoC-based multiprocessor SoCs. In Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP), pages 400-404, 2014. |
| • | Mehdi Dehbashi and Görschwin Fey. SAT-based speedpath debugging using waveforms. In IEEE European Test Symposium (ETS), pages 63-68, 2014. |
| • | Mehdi Dehbashi and Görschwin Fey. Debug automatisierung für logische schaltungen unter zeitvariation mittels waveforms. In GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2014. |
| • | Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, and Rolf Drechsler. Behaviour driven development for tests and verification. In Martina Seidl and Nikolai Tillmann, editors, International Conference on Tests and Proofs, volume 8570 of Lecture Notes in Computer Science, pages 61-77. Springer International Publishing, 2014. |
| • | Julia Seiter, Robert Wille, Ulrich Kühne, and Rolf Drechsler. Automatic refinement checking for formal system models. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pages 1-8, 2014. |
| • | Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, and Rolf Drechsler. Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines. In IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, April 23-25, 2014, pages 129-134. IEEE, 2014. |
| • | Rolf Drechsler and Ulrich Kühne. Safe ip integration using container modules. In Electronic System Design (ISED), pages 1-4, 2014. |
2013
| • | Mehdi Dehbashi. Debug Automation from Pre-Silicon to Post-Silicon. PhD thesis, University of Bremen, 2013. |
| • | Mehdi Dehbashi, Andre Sülflow, and Görschwin Fey. Automated design debugging in a testbench-based verification environment. Microprocessors and Microsystems (MICPRO), 37(2):206-217, 2013. |
| • | Mehdi Dehbashi and Görschwin Fey. Debug automation for logic circuits under timing variations. IEEE Design and Test of Computers (DT), 30(6):60-69, 2013. |
| • | Mehdi Dehbashi and Görschwin Fey. Efficient automated speedpath debugging. In IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 48-53, 2013. |
| • | Mehdi Dehbashi and Görschwin Fey. Towards debug automation for timing bugs at RTL. In GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2013. |
| • | Melanie Diepenbeck, Mathias Soeken, Daniel Große, and Rolf Drechsler. Towards automatic scenario generation from coverage information. In Proceedings of the International Workshop on Automation of Software Test (AST), pages 82-88, May 2013. |
| • | Julia Seiter, Robert Wille, Mathias Soeken, and Rolf Drechsler. Determining relevant model elements for the verification of UML/OCL specifications. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pages 1189-1192, 2013. |
2012
| • | Mehdi Dehbashi and Görschwin Fey. Automated debugging from pre-silicon to post-silicon. In IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 324-329, 2012. |
| • | Mehdi Dehbashi and Görschwin Fey. Automated post-silicon debugging of failing speedpaths. In Asian Test Symposium (ATS), pages 13-18, 2012. |
| • | Mehdi Dehbashi and Görschwin Fey. Application of timing variation modeling to speedpath diagnosis. In System, Software, SoC and Silcon Debug Conference (S4D), pages 34-37, 2012. |
| • | Mehdi Dehbashi and Görschwin Fey. Automated debugging from pre-silicon to post-silicon. In GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2012. |
| • | Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, and Anand Raghunathan. Functional analysis of circuits under timing variations. In IEEE European Test Symposium (ETS), page 177, 2012. |
| • | Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, and Anand Raghunathan. Functional analysis of circuits under timing variations. In edaWorkshop, pages 45-50, 2012. |
| • | Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, and Anand Raghunathan. On modeling and evaluation of logic circuits under timing variations. In EUROMICRO Symposium on Digital System Design (DSD), pages 431-436, 2012. |
| • | Melanie Diepenbeck, Mathias Soeken, Daniel Große, and Rolf Drechsler. Behavior driven development for circuit design and verification. In Proceedings of the International Workshop on High Level Design Validation and Test Workshop (HLDVT), pages 9-16, Nov 2012. |
| • | Julia Seiter, Mathias Soeken, Robert Wille, and Rolf Drechsler. Property checking of quantum circuits using quantum multiple-valued decision diagrams. In Reversible Computation, 4th International Workshop, RC 2012, Copenhagen, Denmark, July 2-3, 2012. Revised Papers, pages 183-196, 2012. |
