Program


DOWNLOAD
A4-Version

(deutsch)

Sonntag, 27. Februar 2022

18:00 - 20:00 Registration & Dinner
20:00 - 21:30 Public Session GI/GMM/ITG-Fachgruppe
"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"

Montag, 28. Februar 2022


8:00 - 9:00 Registration
9:00 - 9:10 Opening
9:10 - 10:10 Keynote 1
Can test bridge the last gap between safety and security?
Andreas Lentz, NXP Semiconductors

Moderation: René Krenz-Baath, Hochschule Hamm-Lippstadt
10:10 - 10:40 Coffee break
10:40 - 12:20

1

Session 1: Post-Silicon Debug, Verification and Validation

Moderation: JĂĽrgen Alt, Infineon Technologies AG

An ILP-based Global Optimum Test Scheduler for IEEE 1687 Multi-Power Domain Networks
Payam Habiby*, Sebastian Huhn*^ & Rolf Drechsler*^
*DFKI GmbH, ^Universität Bremen

A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning
Yiwen Liao*, Jochen Rivoir, Raphael Latty & Bin Yang*
*Unversität Stuttgart, ^Advantest Europe GmbH

System Level Verification of Analog/Mixed-Signal Systems using Metamorphic Relations
Muhammad Hassan* & Rolf Drechsler*^
*DFKI GmbH, ^Universität Bremen

From SysML to Virtual Prototypes for use in Verification and Validation
Thomas Nirmaier*, Manuel Harrant*, Rainer Menes*, Marc Huppmann*, Vlad Cristian Dumitrica^ & Wendy You*
*Infineon Technologies AG, ^Infineon Technologies Romania
12:20 - 13:15 Lunch
13:15 - 14:30

2

Session 2: Characterizing Silicon

Moderation: Jürgen Schlöffel, Siemens Digital Industries Software

A Layout-aware Selection Flow for Functional Path Ring Oscillators
Tobias Kilian*, Heiko Ahrens^, Daniel Tille^, Martin Huch^ & Ulf Schlichtmann*
*Technische Universität München, ^Infineon Technologies AG

Messumgebung zur mixed-signal Echtzeit-Parametererfassung bei Lebensdauertests
Bjoern Bieske*, Dagmar Kirsten^, Ingo Gryl* & Michael Meister*
* IMMS GmbH, ^ X-Fab GmbH

An Automated Test Approach for Measuring the Degradation of Individual Contacts in BGA Sockets
David Riehl, Philipp Gebhart & Klaus Hofmann
Technische Universität Darmstadt
14:30 - 15:00 Pitch Session 1
15:00 - 16:00 Poster-Session 1 & Coffee break

Moderation: Matthias Sauer, Advantest Europe GmbH

Impact of Temperature on the Faulty Behavior of Defective Memristive Devices: Preliminary Results
Thiago Santos Copetti &Leticia Bolzani Poehls
RWTH Aachen Universität Aachen

Vereinfachung der Bestimmung von 4-Bit Fehlern fĂĽr BCH Codes
Christian Schulz-Hanke
Universität Potsdam

Test-Strategy Design based on System-Availability for Handling of Permanent Faults inside FPGAs
Florian Rittner*, Patrik Rác*, Jörg Robert^ & Albert Heuberger*
*Friedrich-Alexander-Universität Erlangen-Nürnberg , ^Technische Universität Ilmenau

Model-Based Analysis of Accelerated Lifetime Test Data of Off-Line LED Drivers
Ferdinand Keil, Simon Benkner, Tran Quoc Khanh & Klaus Hofmann
Technische Universität Darmstadt
16:00 - 17:15

3

Session 3: Yield

Moderation: Heinz Riener, Cadence

Ausbeute Vorhersage und Parametergrenzen
Rebecca Busch, Peter Stich & Michael Wahl
Universität Siegen

Machine Learning for Reliability-Aware, yet Confidential Standard Cell Characterization
Florian Klemme & Hussam Amrouch
Universität Stuttgart

Effective Layout-aware Fault Criteria for Adaptive Testing - A Case Study
Stephan EggersglĂĽĂź & Andreas Glowatz
Siemens EDA
17:15 - 17:45 Pause

Dienstag, 01. März 2022

9:00 - 10:00 Keynote 2
Model-based resilience in the context of complex socio-technical systems
Frank Sill Torres, German Aerospace Center (DLR)

Moderation: Melanie Schillinsky, NXP Semiconductors
10:00 - 10:30 Pitch Session 2
10:30 - 11:30 Poster-Session 2 & Coffee break

Moderation: Mario Schölzel, Hochschule Nordhausen

An Approach to Verification of ATE Power Supply and Signal Integrity using Virtual-DUT
Saeid Yazdani, Werner Wolz, Christian Schott, Franziska Mayer, Enrico Billich & Ulrich Heinkel
Technische Universität Chemnitz

Covering the Long Tail Test Patterns by System-Level Test
Nourhan Elhamawy*, Jens Anders*, Ilia Polian* & Matthias Sauer^
*Universität Stuttgart, ^Advantest Europe GmbH

Modeling Bio-Electronic Systems
Joseline Heuer*, Rene Krenz-Baath* & Roman Obermaisser^
*Hochschule Hamm-Lippstadt, ^Universität Siegen

Self-Learning Tuning for Post-Silicon Validation
Peter Domanski*, Dirk Pflüger*, Jochen Rivoir^ & Raphaël Latty^
* Universität Stuttgart, ^ Advantest Europe GmbH
11:30 - 12:45

4

Session 4: Formal Methods in Test

Moderation: Frank Nolting, Synopsys GmbH

Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
Marcel Merten^, Sebastian Huhn*^ & Rolf Drechsler*^
*DFKI GmbH, ^Universität Bremen

Constraints for Automatic, Generic SBST Generation for RISC-V Using SAT-Solving
Tobias Faller, Markus Schwörer, Philipp Scholl, Tobias Paxian & Bernd Becker
Universität Freiburg

Runtime Monitoring of c-LTL Specifications on FPGAs using HLS
Gianluca Martino & Görschwin Fey
Technische Universität Hamburg
12:45 - 13:00 Closing
13:00 - 13:30 Lunch