17th International Workshop on Boolean Problems | Times are in CEST (Central European Summer Time)

Program

University of Bremen | MZH 1090

Wednesday | September 16


17:00 - 18:30 Welcome Reception


Thursday | September 17


08:30 – 09:00 Registration

09:00 – 09:15 Opening and Welcome

09:15 – 10:15 | Keynote 1
Chair: Chandan Kumar Jha

Frank Sill Torres
German Aerospace Center (DLR)
University of Bremen

Resilience of Cyber-physical Systems



10:15 – 10:45 | Coffee Break

10:45 – 12:15 | Session 1
Chair: Oliver Keszöcze

Incremental Autosymmetry Testing of Regular Functions through AND-Inverter Graphs
Gianmarco Cuciniello, Anna Bernasconi, and Valentina Ciriani

How Do BMC Formulas Evolve? An Empirical Study of SAT Feature Dynamics During Incremental Unrolling
Satyam Shubham and Ansuman Banerjee

Exploiting Functional Characteristics to Optimize Montgomery Arithmetic Hardware Design
Ritaja Das, Bhavani Sampathkumar, Priyank Kalla and Florian Enescu


12:15 – 13:45 | Lunch

13:45 - 14:45 | Session 2
Chair: Petr Fišer

PolySAT: A Fast Cache-SAT Implementation for Solving Boolean Problems with Parameterized Complexity
Luca Müller, Marten Gollücke, and Rolf Drechsler

Rule- and Aim-based Policy to Solve the Game 2048
Bernd Steinbach
14:45 - 15:15 | Coffee Break

15:15 - 16:15 | Session 3
Chair: Görschwin Fey

Formal Verification of Integer Modulo Arithmetic Circuits
Ritaja Das, Bhavani Priya Sampath Kumar, Priyank Kalla and Florian Enescu
The D-metric Revisited: SAT-Based Way to Calculate the Design Diversity
Michal Žáček, Petr Fišer and Jan Schmidt


16:30 - 18:00 | Social Event | Part 1
Universum Bremen

18:30 - 22:00 | Social Event | Part 2
Barbecue Buffet at Restaurant “Waldbühne”

Friday | September 18


9:00 - 10:00 | Keynote 2
Chair: Bernhard Berger

Ahmed Hemani
KTH Royal Institute of Technology

SiLago – A Lego Inspired Design Framework for CMOS and Beyond CMOS



10:00 - 10:30 | Coffee Break

10:30 - 12:00 | Session 4
Chair: Bernd Steinbach

Adaptable Mealy Machine Models for Self-Explainable Systems
Franziska-Sophie Göttsch and Goerschwin Fey
Evaluation of Hardware Multiplier Families for Modulo 3329 Multiplication
Danila Gorodecky, Tsutomu Sasao, and Leonel Sousa

Low-level optimizations in high-level HDLs: Is there a benefit?
Oliver Keszocze, Tjark Petersen, Arved Friedemann and Matthias Bo Stuart


12:00 - 12:15 | Announcements / Closing Remarks

12:15 - 14:00 | Lunch