![]() ![]() | Slot for adding control lines automatically |
![]() ![]() | Contains the result data for read_pla_to_bdd |
![]() ![]() | Collection for buses |
![]() ![]() | Main circuit class |
![]() ![]() | Helper class for adding lines in an easier way |
![]() ![]() | Settings for copy_metadata |
![]() ![]() | A gate simulation implementation of gate_simulation_func |
![]() ![]() | Generic class for the create_image function (Template Design Pattern) |
![]() ![]() ![]() | Implementation of create_image_settings for generating LaTeX code using PsTricks |
![]() ![]() ![]() | Implementation of create_image_settings for generating LaTeX code using TikZ |
![]() ![]() | Concrete re-synthesis functor for the revkit::line_reduction algorithm |
![]() ![]() | Target Tag for Fredkin gates |
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![]() ![]() ![]() | Functor class for interfacing algorithms |
![]() ![]() | Represents a gate in a circuit |
![]() ![]() ![]() | Wrapper for a gate to filter some lines |
![]() ![]() | Calculates the gate costs |
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![]() ![]() ![]() | This class represents a tree based on a Boost.Graph |
![]() ![]() | Calculates the line costs |
![]() ![]() | Window Selection functor based on Line Window Selection |
![]() ![]() | Measure Method for timer |
![]() ![]() | Target Tag for Modules |
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![]() ![]() ![]() | Class for program options on top of the Boost.Program_Options library |
![]() ![]() | Pattern file for sequential simulation |
![]() ![]() | Target Tag for Peres gates |
![]() ![]() | Settings for print_circuit function |
![]() ![]() | Settings for print_statistics |
![]() ![]() | Functor for the timer class which prints the run-time to an output stream |
![]() ![]() | Property Map for storing settings and statistical information |
![]() ![]() | Functor for the timer class which assigns the run-time to a property map |
![]() ![]() | Calculates the quantum costs |
![]() ![]() | Settings for read_pla function |
![]() ![]() | Functor for the timer class which assigns the run-time to a given variable |
![]() ![]() | Re-synthesis optimization (Wrapper for window_optimization) |
![]() ![]() | Base class for actions on the revlib_parser |
![]() ![]() ![]() | Implementation of revlib_processor to construct a circuit |
![]() ![]() ![]() | Implementation of revlib_processor to construct a reversible_truth_table |
![]() ![]() | Window Selection functor based on Shift Window Selection |
![]() ![]() | Represents a circuit |
![]() ![]() | Default gate-wise decomposition |
![]() ![]() | Represents a sub-circuit |
![]() ![]() | Helper class for adding lines in an easier way |
![]() ![]() | A generic timer class |
![]() ![]() | Target Tag for Toffoli gates |
![]() ![]() | Calculates the transistor costs |
![]() ![]() | Represents a truth table |
![]() ![]() | Target Tag for V gates |
![]() ![]() | Target Tag for V+ gates |
![]() ![]() | Cubes reordering strategy as proposed in [FTR07] |
![]() ![]() | Settings for write_blif |
![]() ![]() | Settings for write_realization function |
![]() ![]() | Settings for write_specification |
![]() ![]() | Settings for write_verilog |