Publications [SWD:2010] M. Soeken, R. Wille, and R. Drechsler. Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition. In International Design and Test Workshop, 2010.     [WSD:2010] R. Wille, M. Soeken, and R. Drechsler. Reducing the number of lines in reversible circuits. In Design Automation Conf., 2010. Download     [MWD:2010] D. M. Miller, R. Wille, and R. Drechsler, Reducing Reversible Circuit Cost by Adding Lines, International Symposium on Multiple-Valued Logic, pages 647, 2010. Download     [SWDD:2010] M. Soeken, R. Wille, G. W. Dueck, and R. Drechsler. Window optimization of reversible and quantum circuits. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010. Download     [WD:2009] R. Wille and R. Drechsler. BDD-based synthesis of reversible logic for large functions. In Design Automation Conf., pages 270-275, 2009. Download     [GWDD:2009] D. Große, R. Wille, G. W. Dueck, and R. Drechsler. Exact multiple control Toffoli network synthesis with SAT techniques. IEEE Trans. on CAD, 28(5):703-715, 2009.     [WGDD:2009] R. Wille, D. Große, G. Dueck, and R. Drechsler. Reversible logic synthesis with output permutation. In VLSI Design, pages 189-194, 2009. Download     [WGMD:2009] R. Wille, D. Große, D. M. Miller, and R. Drechsler. Equivalence checking of reversible circuits. In Int'l Symp. on Multi-Valued Logic, pages 324-330, 2009. Download     [FTR:2007] K. Fazel, M. Thornton, and J. Rice. ESOP-based Toffoli gate cascade generation. In IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pages 206-209, 2007.     [MDM:2007] D. Maslov, G. W. Dueck, and D. M. Miller. Techniques for the synthesis of reversible Toffoli networks. ACM Trans. on Design Automation of Electronic Systems, 12(4), 2007.     [ES:2004] N. Een and N. Sörensson. An extensible {SAT} solver. In SAT 2003, volume 2919 of LNCS, pages 502--518, 2004.     [MMD:2003] D. M. Miller, D. Maslov, and G. W. Dueck. A transformation based algorithm for reversible logic synthesis. In Design Automation Conf., pages 318-323, 2003.     [MD:2003] D. Maslov and G. Dueck. Improved quantum cost for n-bit Toffoli gates. Electronics Letters, 39(25):1790-1791, 11 2003.     [Som:2001] F. Somenzi. CUDD: CU Decision Diagram Package Release 2.3.1. University of Colorado at Boulder, 2001.     [BBC+:95] A. Barenco, C. H. Bennett, R. Cleve, D. DiVinchenzo, N. Margolus, P. Shor, T. Sleator, J. Smolin, and H. Weinfurter. Elementary gates for quantum computation. The American Physical Society, 52:3457-3467, 1995.      back