File List
Here is a list of all documented files with brief descriptions:
o*active_controls.hppSlot for adding control lines automatically
o*add_circuit.hppPrepending, inserting and appending circuits to another circuit
o*add_gates.hppAdding typical gates to a circuit
o*add_line_to_circuit.hppAdd a line to a circuit with specifying all meta-data
o*adding_lines.hppAdding Lines Optimization
o*bdd_synthesis.hppBDD Based Synthesis
o*bus_collection.hppBus Collection
o*circuit.hppCircuit class
o*circuit_hierarchy.hppReturns the hierarchy of a circuits by its modules
o*circuit_to_truth_table.hppGenerates a truth table from a circuit
o*clear_circuit.hppClears a circuit
o*control_lines.hppGets the control lines of a gate
o*copy_circuit.hppCopies a circuit
o*costs.hppCost calculation for circuits
o*create_image.hppLaTeX functions for printing circuits
o*create_simulation_pattern.hppCreate simulation pattern for sequential simulation
o*embed_truth_table.hppEmbedding of an irreversible specification
o*equivalence_check.hppSAT-based equivalence check (respects garbage outputs and constant inputs)
o*esop_synthesis.hppESOP Based Synthesis
o*exact_synthesis.hppExact Synthesis of Reversible Networks
o*expand_circuit.hppExpand a circuit on the base of a sub circuit
o*extend_truth_table.hppRemoves the Don't Care Values of a binary truth table
o*find_lines.hppFinds empty and non-empty lines in circuits and gates
o*flatten_circuit.hppFlattens a circuit with modules
o*fully_specified.hppDetermines whether a truth_table is fully specified
o*functor.hppGeneric Functor Implementation based on Boost.Function
o*gate.hppGate class
o*kfdd_synthesis.hppKFDD Based Synthesis
o*line_reduction.hppLine Reduction Optimization
o*lnn_optimization.hppLinear nearest Neighbor
o*optimization.hppGeneral Optimization type definitions
o*partial_simulation.hppSimulation considering constant inputs and garbage outputs
o*pattern.hppData Structure for Simulation Pattern
o*print_circuit.hppConsole output of a circuit
o*print_statistics.hppPrint statistics about a circuit
o*program_options.hppEasier access to program options
o*properties.hppProperty Map Implementation for Algorithms
o*quantum_decomposition.hppQuantum Decomposition of Reversible Circuits
o*read_pattern.hppParser for Simulation pattern
o*read_pla.hppReads a specification from a PLA file
o*read_pla_to_bdd.hppReads a BDD from a PLA file
o*read_realization.hppParser for RevLib realization (*.real) file format
o*read_specification.hppParser for RevLib specification (*.spec) file format
o*reed_muller_synthesis.hppSynthesis algorithm based on Reed Muller Spectra
o*reverse_circuit.hppReverse a circuit
o*revlib_parser.hppRevLib file format parser
o*revlib_processor.hppProcessor which works with the revlib_parser
o*sequential_simulation.hppSequential Simulation considering state inputs
o*simple_simulation.hppVery simple simulation, only efficient for small circuits
o*simulation.hppGeneral Simulation type definitions
o*swop.hppSWOP - Synthesis With Output Permutation
o*synthesis.hppGeneral Synthesis type definitions
o*target_lines.hppGets the target lines of a gate
o*target_tags.hppPredefined target type tags for common gate types
o*timer.hppA generic way for measuring time
o*transformation_based_synthesis.hppTransformation Based Synthesis
o*transposition_based_synthesis.hppA simple synthesis algorithm based on transpositions
o*transposition_to_circuit.hppA simple synthesis algorithm based on transpositions
o*truth_table.hppClass for truth table representation
o*verification.hppGeneral Verification type definitions
o*version.hppReturns RevKit version
o*window_optimization.hppWindow Optimization
o*write_blif.hppWrites a circuit to a BLIF file
o*write_realization.hppGenerator for RevLib realization (*.real) format
o*write_specification.hppWrites a truth table to a RevLib specification file
\*write_verilog.hppWrites a circuit to a Verilog file

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