File List

Here is a list of all documented files with brief descriptions:

active_controls.hpp | Slot for adding control lines automatically |

add_circuit.hpp | Prepending, inserting and appending circuits to another circuit |

add_gates.hpp | Adding typical gates to a circuit |

add_line_to_circuit.hpp | Add a line to a circuit with specifying all meta-data |

adding_lines.hpp | Adding Lines Optimization |

bdd_synthesis.hpp | BDD Based Synthesis |

bus_collection.hpp | Bus Collection |

circuit.hpp | Circuit class |

circuit_hierarchy.hpp | Returns the hierarchy of a circuits by its modules |

circuit_to_truth_table.hpp | Generates a truth table from a circuit |

clear_circuit.hpp | Clears a circuit |

control_lines.hpp | Gets the control lines of a gate |

copy_circuit.hpp | Copies a circuit |

copy_metadata.hpp | |

costs.hpp | Cost calculation for circuits |

create_image.hpp | LaTeX functions for printing circuits |

create_simulation_pattern.hpp | Create simulation pattern for sequential simulation |

embed_truth_table.hpp | Embedding of an irreversible specification |

equivalence_check.hpp | SAT-based equivalence check (respects garbage outputs and constant inputs) |

esop_synthesis.hpp | ESOP Based Synthesis |

exact_synthesis.hpp | Exact Synthesis of Reversible Networks |

expand_circuit.hpp | Expand a circuit on the base of a sub circuit |

extend_truth_table.hpp | Removes the Don't Care Values of a binary truth table |

find_lines.hpp | Finds empty and non-empty lines in circuits and gates |

flatten_circuit.hpp | Flattens a circuit with modules |

fully_specified.hpp | Determines whether a truth_table is fully specified |

functor.hpp | Generic Functor Implementation based on Boost.Function |

gate.hpp | Gate class |

kfdd_synthesis.hpp | KFDD Based Synthesis |

line_reduction.hpp | Line Reduction Optimization |

lnn_optimization.hpp | Linear nearest Neighbor |

optimization.hpp | General Optimization type definitions |

partial_simulation.hpp | Simulation considering constant inputs and garbage outputs |

pattern.hpp | Data Structure for Simulation Pattern |

print_circuit.hpp | Console output of a circuit |

print_statistics.hpp | Print statistics about a circuit |

program_options.hpp | Easier access to program options |

properties.hpp | Property Map Implementation for Algorithms |

quantum_decomposition.hpp | Quantum Decomposition of Reversible Circuits |

read_pattern.hpp | Parser for Simulation pattern |

read_pla.hpp | Reads a specification from a PLA file |

read_pla_to_bdd.hpp | Reads a BDD from a PLA file |

read_realization.hpp | Parser for RevLib realization (*.real) file format |

read_specification.hpp | Parser for RevLib specification (*.spec) file format |

reed_muller_synthesis.hpp | Synthesis algorithm based on Reed Muller Spectra |

reverse_circuit.hpp | Reverse a circuit |

revlib_parser.hpp | RevLib file format parser |

revlib_processor.hpp | Processor which works with the revlib_parser |

sequential_simulation.hpp | Sequential Simulation considering state inputs |

simple_simulation.hpp | Very simple simulation, only efficient for small circuits |

simulation.hpp | General Simulation type definitions |

swop.hpp | SWOP - Synthesis With Output Permutation |

synthesis.hpp | General Synthesis type definitions |

target_lines.hpp | Gets the target lines of a gate |

target_tags.hpp | Predefined target type tags for common gate types |

timer.hpp | A generic way for measuring time |

transformation_based_synthesis.hpp | Transformation Based Synthesis |

transposition_based_synthesis.hpp | A simple synthesis algorithm based on transpositions |

transposition_to_circuit.hpp | A simple synthesis algorithm based on transpositions |

truth_table.hpp | Class for truth table representation |

verification.hpp | General Verification type definitions |

version.hpp | Returns RevKit version |

window_optimization.hpp | Window Optimization |

write_blif.hpp | Writes a circuit to a BLIF file |

write_realization.hpp | Generator for RevLib realization (*.real) format |

write_specification.hpp | Writes a truth table to a RevLib specification file |

write_verilog.hpp | Writes a circuit to a Verilog file |

Generated on Tue Apr 16 2013 08:12:02 for RevKit by 1.8.3.1