This page gives an outline of all components in the libraries.


gateGate class
circuitCircuit class
functorGeneric Functor Implementation based on Boost.Function.
patternData Structure for Simulation Pattern
propertiesProperty Map Implementation for Algorithms
target_tagsPredefined target type tags for common gate types new features
truth_tableClass for truth table representation
versionReturns RevKit version
active_controlsSlot for adding control lines automatically
add_circuitPrepending, inserting and appending circuits to another circuit
add_gatesAdding typical gates to a circuit
add_line_to_circuitAdd a line to a circuit with specifying all meta-data
circuit_hierarchyReturns the hierarchy of a circuits by its modules
circuit_to_truth_tableGenerates a truth table from a circuit
clear_circuitClears a circuit
control_linesGets the control lines of a gate
copy_circuitCopies a circuit
copy_metadataSettings for copy_metadata
create_simulation_patternCreate simulation pattern for sequential simulation
expand_circuitExpand a circuit on the base of a sub circuit
extend_truth_tableRemoves the Don't Care Values of a binary truth table
find_linesFinds empty and non-empty lines in circuits and gates
flatten_circuitFlattens a circuit with modules
fully_specifiedDetermines whether a truth_table is fully specified
reverse_circuitReverse a circuit
target_linesGets the target lines of a gate
transposition_to_circuitA simple synthesis algorithm based on transpositions new features
create_imageLaTeX functions for printing circuits
print_circuitConsole output of a circuit
print_statisticsPrint statistics about a circuit
read_patternParser for Simulation pattern
read_realizationParser for RevLib realization (*.real) file format
read_specificationParser for RevLib specification (*.spec) file format
read_plaReads a specification from a PLA file
revlib_parserRevLib file format parser
revlib_processorProcessor which works with the revlib_parser
write_blifWrites a circuit to a BLIF file new features
write_realizationGenerator for RevLib realization (*.real) format
write_specificationWrites a truth table to a RevLib specification file
write_verilogWrites a circuit to a Verilog file
bus_collectionBus Collection
costsCost calculation for circuits
program_optionsEasier access to program options
timerA generic way for measuring time


adding_linesAdding Lines Optimization
line_reductionLine Reduction Optimization
window_optimizationWindow Optimization
bdd_synthesisBDD Based Synthesis
embed_truth_tableEmbedding of an irreversible specification
esop_synthesisESOP Based Synthesis
exact_synthesisExact Synthesis of Reversible Networks
kfdd_synthesisKFDD Based Synthesis
quantum_decompositionQuantum Decomposition of Reversible Circuits
reed_muller_synthesisSynthesis algorithm based on Reed Muller Spectra new features
swopSWOP - Synthesis With Output Permutation
transformation_based_synthesisTransformation Based Synthesis
transposition_based_synthesisA simple synthesis algorithm based on transpositions new features
partial_simulationSimulation considering constant inputs and garbage outputs
sequential_simulationSequential Simulation considering state inputs
simple_simulationVery simple simulation, only efficient for small circuits
equivalence_checkSAT-based equivalence check (respects garbage outputs and constant inputs)

Generated on Tue Apr 16 2013 08:12:02 for RevKit by doxygen