Embedded Tutorials


Tutorial 1
Tutorial 2
Tutorial 3



1

Krishnendu CHAKRABARTY

Duke University - USA

Yu Wang

Tsinghua University - China

Design of Fault-Tolerant Neuromorphic Computing Systems


TUTORIAL SUMMARY:
This tutorial will first introduce ETS attendees to the exciting and emerging area of neuromorphic computing systems for machine learning hardware. First, the presenters will describe RRAM-based crossbars and their role in neuromorphic computing systems. Following this, the need for testing and fault tolerance will be motivated in light of imperfect fabrication technologies, as well as technology limitations such as write endurance in RRAM cells. Fault models and test solutions will be presented. Subsequently, techniques for online testing and fault-tolerant training will be described.

SHORT BIO | Krishnendu CHAKRABARTY:
Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the William H. Younger Distinguished Professor and Department Chair of Electrical and Computer Engineering, and Professor of Computer Science at Duke University. Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award (2015), the ACM Transactions on Design Automation of Electronic Systems Best Paper Award (2017), and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award, the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award, and the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur. He is a Research Ambassador of the University of Bremen (Germany) and a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany. He is a 2018 recipient of the Japan Society for the Promotion of Science (JSPS) Fellowship in the "Short Term S" category (typically awarded to eminent researchers who have won the Nobel Prize or similar honors). He is the Editor-in-Chief (EIC) of IEEE Transactions on VLSI Systems, and he is a past EIC of IEEE Design & Test and ACM Journal on Emerging Technologies in Computing Systems. Professor Chakrabarty has given over 300 invited, keynote, and plenary talks. He has also presented 50 tutorials at major international conferences, including ITC, DAC, DATE, ICCAD, ISCAS. He has presented embedded tutorials at ETS twice in previous years. Prof. Chakrabarty is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He served as a Distinguished Visitor of the IEEE Computer Society (2005-2007, 2010-2012), a Distinguished Lecturer of the IEEE Circuits and Systems Society (2006-2007, 2012-2013), and an ACM Distinguished Speaker (2008-2016).

SHORT BIO | Yu WANG:
Yu Wang received his B.S. degree in 2002 and Ph.D. degree (with honors) in 2007 from Tsinghua University, Beijing. He is currently a tenured Associate Professor with the Department of Electronic Engineering, Tsinghua University. His research interests include brain inspired computing, application specific hardware computing, parallel circuit analysis, and power/reliability aware system design methodology. Dr. Wang has authored and coauthored over 170 papers in refereed journals and conferences. He has received Best Paper Award in FPGA 2017, ISVLSI 2012, and Best Poster Award in HEART 2012 with 7 Best Paper Nominations (ASPDAC 2014, ASPDAC 2012, 2 in ASPDAC 2010, ISLPED 2009, CODES 2009). He is a recipient of IBM X10 Faculty Award in 2010. He served as TPC chair for ICFPT 2011 and Finance Chair of ISLPED 2012-2016, and served as program committee member for leading conferences in these areas, including top EDA conferences such as DAC, DATE, ICCAD, ASP-DAC, and top FPGA conferences such as FPGA and FPT. Currently he serves as Co-Editor-in-Chief for ACM SIGDA E-Newsletter, Special Issue Editor for Elsevier Microelectronic Journal, Associate Editor for IEEE Transactions on CAD, and Journal of Circuits, Systems, and Computers. He also serves as guest editor for Integration, the VLSI Journal and IEEE Transactions on Multi-Scale Computing Systems. Yu Wang also received The Natural Science Fund for Outstanding Youth Fund in 2016, and is the co-founder of Deephi Tech (valued over 150M USD), which is a leading deep-learning processing platform provider. He is a Distinguished Speaker of ACM and well-known for his many pioneering contributions to machine learning hardware.

2

Vladimir Rozic

KU Leuven ESAT/COSIC

Viktor Fischer

Hubert Curien Laboratory, Jean Monnet University

Design and Testing Methodologies for True Random Number Generators Towards Industry Certification


TUTORIAL SUMMARY:
The objective of this tutorial is to provide insight on the design, evaluation and testing of modern True Random Number Generators (TRNGs) aimed towards certification. We will discuss aspects related to each of these stages by means of two illustrative TRNG designs: PLL-TRNG and DC-TRNG. Topics covered in the tutorial will include: the importance of formal security testing based on stochastic models of the entropy source, the development of embedded tests to detect failures, the implementation and evaluation of TRNGs in dedicated FPGA platforms, and their robustness to environmental and/or physical modifications. The results presented in this tutorial have been developed in the framework of the EU H2020 project HECTOR (Hardware Enabled Crypto and Randomness, grant agreement no. 644052, www.hector-project.eu).

SHORT BIO | Vladimir Rozic:
Dr. Ir. Vladimir Rozic received the Bachelor's degree of Electrical Engineering from the University of Belgrade (Serbia) in 2007 and a PhD in Engineering Science from the KU Leuven (Belgium) in 2016. He is currently a postdoctoral researcher at the research group COSIC. His main research interests are related to embedded security with a special focus on hardware random number generators, physically unclonable functions and design of secure cryptographic chips. Vladimir has research experience in various national and international research projects related

SHORT BIO | Viktor Fischer:
Viktor Fischer received the M.S. and Ph.D. degrees in electrical engineering from the Technical University of Košice, Košice, Slovakia. From 1981 to 1991, he held an Assistant Professor position with the Department of Electronics, Technical University of Košice. From 1991 to 2006, he was a Part-Time Invited Professor with the University of St.- Étienne, St.-Étienne, France. From 1999 to 2006, he was a Consultant with Micronic, Trebejov, Slovakia, oriented in hardware data security systems. Since 2006, he has been a Full-Time Professor with the University of Saint-Étienne. His current research interests include cryptographic engineering, secure embedded systems, cryptographic processors, and especially, true random number generators embedded in logic devices. Dr. Fischer is the Co-Founder and a Senior Member of the CryptArchi Club.

3

Haralampos-G. Stratigopoulos

Sorbonne Université, CNRS, Laboratoire d'Informatique de Paris 6 (LIP6), Paris, France

Machine learning applications in IC testing


TUTORIAL SUMMARY:
This tutorial seeks to elucidate the utility of machine learning in semiconductor testing. Relevant concepts from machine learning theory will be introduced and agglomerated with the current test practice, showcasing their effectiveness on actual case studies with industrial data. A concise and comprehensive survey of the relevant literature will be provided, organized around test cost reduction, fault diagnosis, and outlier detection. We will also briefly mention other test problems for which machine learning can come to the rescue, including self-calibration, yield leaning, exploiting wafer-level spatial correlations and lot-level spatiotemporal correlations, etc. As there is already a large body of work on machine learning applications in test, we will discuss why these techniques have not yet fully materialize. We will argue that the primary reason is the error risk and we will discuss error moderation techniques that add confidence to a machine learning-based test solution. Finally, we will discuss emerging applications of machine learning in test, including adaptive test, neuromorphic built-in self-test, and deep learning.

SHORT BIO
Haralampos-G. Stratigopoulos received the Diploma in electrical and computer engineering from the National Technical University of Athens, Greece, in 2001 and the Ph.D. in electrical engineering from Yale University, USA, in 2006. From October 2007 to May 2015 he was a Researcher with the French National Center for Scientific Research (CNRS) at TIMA Laboratory, Université Grenoble Alpes, Grenoble, France. Currently he is a Researcher with the CNRS at LIP6 Laboratory, Sorbonne Université, Paris, France. His main research interests are in the areas of design-for-test and built-in self-test for analog, mixed-signal, RF circuits and systems, computer-aided design, machine learning applications in manufacturing and test, and hardware security. He was the General Chair of the 2015 IEEE International Mixed-Signal Testing Workshop (IMSTW) and the Program Chair of the 2017 IEEE European Test Symposium (ETS). He has served on the Technical Program Committees of Design, Automation, and Test in Europe Conference (DATE), IEEE International Conference on Computer-Aided Design (ICCAD), IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE International Test Conference (ITC) and several others international conferences. He is an Associate Editor of Springer Journal of Electronic Testing: Theory & Applications, IEEE Design & Test Magazine, and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He received the Best Paper Award in the 2009, 2012, and 2015 IEEE European Test Symposium (ETS).

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