2021 International Conference On
Computer-Aided Design


The Premier Conference Devoted to Technical Innovations in
Electronic Design Automation
Virtual Technical Program:
November 1-4, 2021
Networking In-Person:
November 5, 2021




1.1 System Design
  • System-level specification, modeling, simulation, design flows
  • System-level issues for 3D integration
  • System-level design case studies and applications
  • HW/SW co-design, co-simulation, co-optimization, and co-exploration, platforms for emulation and rapid prototyping
  • Micro-architectural transformation
  • Multi-/many-core processor, GPU and heterogeneous SoC
  • Memory and storage architecture and system synthesis
  • System communication architecture, Network-on-chip design
  • Modeling, simulation, high-level synthesis, power/performance analysis, programming of heterogeneous computing platforms
  • Application driven system design for big data
  • Analysis and optimization of data centers
1.2 Embedded, Cyber-Physical (CPS), IoT Systems and Software
  • AI and machine learning for embedded systems
  • HW/SW co-design for embedded systems
  • Compute, memory, storage, interconnect for embedded systems
  • Domain-specific accelerators
  • Energy/power management and energy harvesting
  • Real-time software and systems
  • Middleware, virtual machines, and runtime support
  • Dependable, safe, secure, trustworthy embedded systems
  • Embedded software: compilation, optimization, testing
  • CAD for IoT, edge and fog computing
  • Modeling, analysis, verification of CPS systems
  • Green computing (smart grid, energy, solar panels, etc.)
  • CAD for application domains including wearables, health care, autonomous systems, smart cities
1.3 Neural Networks and Deep Learning
  • Hardware and architecture for neural networks
  • Compilers for deep neural networks
  • Design method for learning on a chip
  • System-level design for (deep) neural computing
  • Neural network acceleration including GPU and ASICs
  • Safe and secure machine learning
  • Hardware accelerators for Artificial Intelligence
1.4 Reconfigurable Computing
  • Novel reconfigurable architectures (FPGA, CGRA, etc.)
  • Neural network acceleration on reconfigurable accelerators
  • High-level synthesis on reconfigurable architectures
  • Compilers for reconfigurable architectures
  • Reconfigurable fabric security
  • HW/SW prototyping and emulation on FPGAs
  • Post-synthesis optimization for FPGAs
  • FPGA-based prototyping for analog, mixed-signal, RF systems
1.5 Hardware Security, Security Architecture and Systems
  • Hardware Trojans, side-channel attacks, fault attacks and countermeasures
  • New physical attack vectors or methods for ASICs
  • Nano electronic security
  • Hardware-based security (CAD for PUF's, RNG, AES etc.)
  • Split Manufacturing for security
  • Supply chain security and anti-counterfeiting
  • Artificial Intelligence for attack prevention systems
  • Design and CAD for security
  • Security implications of CAD
  • Trusted execution environments
  • Privacy-preserving computation
  • Cloud Computing data security
  • Sensor network security
1.6 Low Power and Approximate Computing in System Design
  • Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems
  • Energy- and thermal-aware application mapping and scheduling
  • Energy- and thermal-aware architectures, algorithms
  • Energy- and thermal-aware dark silicon system design
  • Hardware techniques for approximate/stochastic computing
2.1 High-Level, Behavioral, and Logic Synthesis and Optimization
  • High-level/Behavioral/Logic synthesis
  • Technology-independent optimization and technology mapping
  • Functional and logic timing ECO (engineering change order)
  • Resource scheduling, allocation, and synthesis
  • Interaction between logic synthesis and physical design
2.2 Testing, Validation, Simulation, and Verification
  • High-level/Behavioral/Logic modeling, validation, simulation
  • Formal, semi-formal, and assertion-based verification
  • Equivalence and property checking
  • Emulation and hardware simulation/acceleration
  • Post-silicon validation and debug
  • Digital fault modeling and simulation
  • Delay, current-based, low-power test
  • ATPG, BIST, DFT, and compression
  • Memory test and repair
  • Core, board, system, and 3D IC test
2.3 Cell-Library Design, Partitioning, Floorplanning, Placement
  • Cell-library design and optimization
  • Transistor and gate sizing
  • High-level physical design and synthesis
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  • Estimation and hierarchy management
  • 2D and 3D partitioning, floorplanning, and placement
  • Post-placement optimization
  • Buffer insertion and interconnect planning
2.4 Clock Network Synthesis, Routing, and Post-Layout Optimization
  • 2D and 3D clock network synthesis
  • 2D and 3D global and detailed routing
  • Package-/Board-level
  • Chip-package-board co-design
  • Post-layout/-silicon optimization
  • Layout and routing issues for optical interconnects
2.5 Design for Manufacturability and Design for Reliability
  • Process technology characterization, extraction, and modeling
  • CAD for design/manufacturing interfaces
  • CAD for reticle enhancement and lithography-related design
  • Variability analysis and statistical design and optimization
  • Yield estimation and design for yield
  • Physical verification and design rule checking
  • Machine learning for smart manufacturing and process control
  • Analysis and optimization for device-level reliability issues
  • Analysis optimization for interconnect reliability issues
  • Reliability issues related to soft errors
  • Design for resilience and robustness
2.6 Timing, Power and Signal Integrity Analysis and Optimization
  • Deterministic and statistical static timing analysis, optimization
  • Power and leakage analysis and optimization
  • Circuit and interconnect-level low power design issues
  • Power/ground network analysis and synthesis
  • Signal integrity analysis and optimization
2.7 CAD for Analog/Mixed-Signal/RF and Multi-Domain Modeling
  • Analog, mixed-signal, and RF noise modeling, simulation, test
  • Electromagnetic simulation and optimization
  • Device, interconnect and circuit extraction and simulation
  • Behavior modeling of devices and interconnect
  • Package modeling and analysis
  • Modeling of complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc.)
3.1 Bio-inspired and Neuromorphic Computing, Biological Systems and Electronics, and New Computing Paradigms
  • Network and neuron models
  • Devices and hardware for neuromorphic computing
  • Non-von Neumann architecture
  • Event or spike-based hardware systems
  • CAD for biological computing systems
  • CAD for synthetic biology
  • CAD for bio-electronic devices, bio-sensors, MEMS systems
3.2 Nanoscale and Post-CMOS Systems
  • New device structures and process technologies
  • New memory technologies (flash, PCM, STT-RAM, memristor)
  • Nanotechnologies, nanowires, nanotubes, graphene, etc.
  • Quantum computing
  • CAD for mixed-domain (semiconductor, nanoelectronic, MEMS, and electro-optical) devices, circuits, and systems
  • CAD for nanophotonics and optical devices/communication
  • DFM and reliability issues for emerging devices (3D, Nano photonics, non-volatile logic/memory, etc.)


Paper submissions must be made through the online submission system at the ICCAD web site: https://www.softconf.com/l/iccad2021/.
Regular papers will be reviewed as finished papers; preliminary submissions will be at a disadvantage. Research papers with open-source software are highly encouraged where the software will be made publicly available (via GitHub or similar) with the camera-ready version if the paper has been accepted. For protecting the authors' identities in the double-blind review process, please do not include direct link to the non-anonymized software yet in the submitted paper but indicate the open-source contribution on a textural basis only. Authors wanting to share GitHub repositories may want to look into using https://anonymous.4open.science/ which is an open-source tool that helps you to quickly Double-blind your repository.
Authors are asked to submit their work in two stages. In stage one (abstract submission), a title, abstract, and a list of all co-authors must be submitted via the ICCAD web submission site. In stage two (paper submission), the paper itself is submitted whereby the submitted abstract of stage one can still be modified. Authors are responsible for ensuring that their paper submission meets all guidelines, and that the PDF is readable.

The submission abstract deadline is 5:00pm PDT (GMT -07:00) Friday, May 21, 2021. No abstract submissions will be possible after this deadline.
The submission deadline for paper is 5:00pm PDT (GMT -07:00) Friday, May 28, 2021. We always have several authors contact the ICCAD office asking for a deadline extension. Due to the limited review cycle, NO extensions will be granted for ANY reason.

  • All papers must be in PDF format only, with savable text and embedded fonts in included (vector) graphics.
  • Each paper must be no more than 8 pages (including the abstract, figures and tables), double-columned, 9pt or 10pt font. Starting from last year, one page of references is allowed, which does not count towards this 8-page limitation.
  • Your submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, or in the embedded PDF data. References and bibliographic citations to the author(s) own published works or affiliations should be made in the third person.
  • Submissions not adhering to these rules, or determined to be previously published or simultaneously submitted to another conference, or journal, will be summarily rejected. Internal memoranda with full content not publicly available, and with author names not divulged, may be submitted.
IMPORTANT: Final camera-ready versions must be identical to the submitted papers with the following exceptions; inclusion of author names/affiliation, correction of identified errors, addressing reviewer-demanded changes. No other modifications of any kind are allowed including modification of title, change of the author list, reformatting, restyling, rephrasing, removing figures/results/text, etc. The TPC Chairs reserve the right to finally reject any manuscripts not adhering to these rules. A report detailing all the revisions made must be submitted together with the final camera-ready manuscript once any revision is conducted.

Paper templates are available at the IEEE website and authors are recommended to format their papers based on the IEEE template.

Authors will be notified of acceptance on or before Saturday, July 17, 2021. Final paper guidelines will be sent at that time.

The deadline for final papers is Monday, August 16, 2021. Accepted regular papers are allowed six pages plus one page of references in the conference proceedings free of charge. Each additional page (except references) beyond six pages is subject to the page charge at $150.00 per page up to the eight-page plus one page of references. IEEE will hold the copyright for ICCAD 2021 proceedings. Authors of accepted papers must sign an IEEE copyright release form for their paper.

At least one author per accepted regular paper or poster must register by Wednesday, September 1, 2021, at the discounted speakers registration rate. Failure to register will result in your paper being removed from the conference proceedings. In case of a regular paper, IEEE reserves the right to exclude a paper from distribution after the conference (e.g., removal from IEEE Xplore) if the paper is not presented at the conference. Starting from this year, the presentation of a regular paper includes both an oral and a poster presentation. The mandatory poster presentation will, in addition to the regular oral presentation, further stimulate the technical discussions.