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» Using a Two-Dimensional Fault List for Compact Automatic Test Pattern Generation




Author:

Marc Messing, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Workshop:
10th IEEE Latin-American TestWorkshop (LATW)
Reference:

Búzios, Rio de Janeiro, 2009
Hyperlink:

[Link to the Workshop]



» Debug Patterns for Efficient High-level SystemC Debugging




Author:

Frank Rogin, Erhard Fehlauer, Christian Haufe, Sebastian Ohnewald
Workshop:
10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Reference:

Krakau, 2007
Hyperlink:

[Link to the Workshop]



» Instance Generation for SAT-based ATPG




Author:

Daniel Tille, Görschwin Fey, Rolf Drechsler
Workshop:
10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Reference:

Krakau, 2007
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» A framework for reversible circuit complexity




Author:

Mathias Soeken, Nabila Abdessaied, Rolf Drechsler
Workshop:
10th International Workshop on Boolean Problems
Reference:

Freiberg, Germany, 2014, post-print available at arXiv:1407.5878
Hyperlink:

[Link to the Workshop]
PDF:

[click here]
PS:

[click here]



» Induction-based Formal Verification of SystemC TLM Designs




Author:

Daniel Große, Hoang M. Le, Rolf Drechsler
Workshop:
10th International Workshop on Microprocessor Test and Verification (MTV)
Reference:

pp. 101-106, Austin, Texas, 2009
Hyperlink:

[Link to the Workshop]



» Debugging Design Errors by Using Unsatisfiable Cores




Author:

Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Workshop:
11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

pp. 159-168, Freiburg, 2008
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking




Author:

Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Workshop:
11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

pp. 169-178, Freiburg, 2008
Hyperlink:

[Link to the Workshop]



» Ad-Hoc Translations to Close Verilog Semantics Gap




Author:

Christian Haufe, Frank Rogin
Workshop:
11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Reference:

Bratislava, 2008
Hyperlink:

[Link to the Workshop]



» Incremental SAT Instance Generation for SAT-based ATPG




Author:

Daniel Tille, Rolf Drechsler
Workshop:
11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Reference:

pp. 68-73, Bratislava, 2008
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Automatic Fault Localization for SystemC TLM Designs




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
11th International Workshop on Microprocessor Test and Verification (MTV)
Reference:

pp. 35-40, Austin, Texas, 2010
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Towards Unifying Localization and Explanation for Automated Debugging




Author:

Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop:
11th International Workshop on Microprocessor Test and Verification (MTV)
Reference:

pp. 3-8, Austin, Texas, 2010
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization




Author:

Görschwin Fey, Rolf Drechsler
Workshop:
11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2003)
Reference:

pp. 54-60, Hiroshima, 2003
PS:

[click here]



» Equivalence Checking of Reversible Circuits




Author:

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Workshop:
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

2009
Hyperlink:

[Link to the Workshop]



» Increasing the Accuracy of SAT-based Debugging




Author:

Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Workshop:
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

pp. 47-56, Berlin, 2009
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Path-Based Program Repair




Author:

Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop:
12th International Workshop on Formal Engineering approaches to Software Components and Architectures, Satellite event of ETAPS (FESCA'15)
Reference:

pp. 22-32, London, United Kingdoms, 2015
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Design Understanding by Automatic Property Generation




Author:

Rolf Drechsler, Görschwin Fey
Workshop:
12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Reference:

pp.274-281, Kanazawa, 2004
PDF:

[click here]



» ParSyC: An Efficient SystemC Parser




Author:

Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler
Workshop:
12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Reference:

pp. 148-154, Kanazawa, 2004
PDF:

[click here]



» SyReC: A Programming Language for Synthesis of Reversible Circuits




Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop:
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

Dresden, 2010
Hyperlink:

[Link to the Workshop]



» Verifying UML/OCL Models Using Boolean Satisfiability




Author:

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Workshop:
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

pp 57-66, Dresden, 2010
Hyperlink:

[Link to the Workshop]



» Visualization of Diagnosis Results for Design Debugging




Author:

Görschwin Fey, Rolf Drechsler
Workshop:
13th International Workshop on Post-Binary ULSI Systems
Reference:

pp. 1-2, Toronto, 2004
PS:

[click here]



» Designing a RISC CPU in Reversible Logic




Author:

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Workshop:
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

pp. 249-258, Oldenburg, 2011
Hyperlink:

[Link to the Workshop]



» Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction




Author:

Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Workshop:
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

pp. 269-278, Oldenburg, 2011
Hyperlink:

[Link to the Workshop]



» Towards Automatic Property Generation for the Formal Verification of Bus Bridges




Author:

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Workshop:
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

Oldenburg, 2011
Hyperlink:

[Link to the Workshop]



» Documentation Driven Software Development for Embedded Systems




Author:

Beate Muranko, Rolf Drechsler
Workshop:
14. Workshop der Fachgruppe WI-VM der Gesellschaft für Informatik e.V. Vorgehensmodelle und Projektmanagement - Assessment, Zertifizierung, Akkreditierung -
Reference:

München, 2007
PDF:

[click here]



» Automated Feature Localization for Hardware Designs using Coverage Metrics




Author:

Jan Malburg, Alexander Finder, Görschwin Fey
Workshop:
15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference:

pp. 85-96, Kaiserslautern, Germany, 2012
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» CRAVE: An Advanced Constrained Random Verification Environment for SystemC




Author:

Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference:

pp. 37-48, Kaiserslautern, 2012
Software and benchmarks available at www.systemc-verification.org
Hyperlink:

[Link to the Workshop]



» Towards Formal Verification on the System Level




Author:

Rolf Drechsler
Workshop:
15th IEEE International Workshop on Rapid System Prototyping
Reference:

Invited Talk, pp. 2-5, Geneva, 2004
PDF:

[click here]



» Mutation based Feature Localization




Author:

Jan Malburg, Emmanuelle Encrenaz-Tiphene, Görschwin Fey
Workshop:
15th International Workshop on Microprocessor Test and Verification
Reference:

Austin, USA, 2014
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» BDD Circuit Optimization for Path Delay Fault-Testability




Author:

Görschwin Fey, Junhao Shi, Rolf Drechsler
Workshop:
15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Reference:

Timmendorfer Strand, 2003
PS:

[click here]



» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits




Author:

Rolf Drechsler
Workshop:
15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Reference:

Timmendorfer Strand, 2003
PS:

[click here]



» Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen




Author:

Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler
Workshop:
16. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

Rostock, 2013
Hyperlink:

[Link to the Workshop]



» Yet a Better Error Explanation Algorithm




Author:

Heinz Riener, Görschwin Fey
Workshop:
16. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'13)
Reference:

pp.193-194, Rostock, Germany, 2013
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» SyCE: An Integrated Environment for System Design in SystemC




Author:

Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
Workshop:
16th IEEE International Workshop on Rapid System Prototyping (RSP)
Reference:

pp. 258-260, Montreal, 2005
PDF:

[click here]



» A Logic for Cardinality Constraints




Author:

Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
Workshop:
17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference:

Böblingen, Germany, 2014
Hyperlink:

[Link to the Workshop]



» Equivalence Checking on System Level using Stepwise Induction




Author:

Niels Thole, Görschwin Fey
Workshop:
17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference:

Böblingen, Germany, 2014
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Formale Methoden für Alle




Author:

Mathias Soeken, Max Nitze, Rolf Drechsler
Workshop:
17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference:

Böblingen, Germany, 2014
Hyperlink:

[Link to the Workshop]



» Funktionale Abdeckungsanalyse von C-Programmen




Author:

Aljoscha Windhorst, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference:

pp. 201-204, Böblingen, Germany, 2014
Hyperlink:

[Link to the Workshop]



» Technische Dokumentation im V-Modell XT




Author:

Beate Kapturek, Rolf Drechsler
Workshop:
17. Workshop der Fachgruppe WI-VM der Gesellschaft für Informatik e.V.
Reference:

Stuttgart, 2010
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Execution Tracing of C Code for Formal Analysis




Author:

Heinz Riener, Michael Kirkedal Thomsen, Görschwin Fey
Workshop:
18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15)
Reference:

Chemnitz, Germany, 2015
Hyperlink:

[Link to the Workshop]



» Verbesserung der Fehlersuche in inkonsistenten formalen Modellen




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Workshop:
18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15)
Reference:

Chemnitz, Germany, 2015
Hyperlink:

[Link to the Workshop]



» Efficiency of Multi-Valued Encoding in SAT-based ATPG




Author:

Görschwin Fey, Junhao Shi , Rolf Drechsler
Workshop:
18. Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“
Reference:

Titisee, 2006



» Symbolic Error Metric Determination for Approximate Computing




Author:

Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler
Workshop:
19. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'16)
Reference:

Freiburg, Germany, 2016
Hyperlink:

[Link to the Workshop]



» Studies on Integrating SAT-based ATPG in an Industrial Environment




Author:

Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop:
19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Reference:

Erlangen, 2007
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation




Author:

Heinz Riener, Görschwin Fey
Workshop:
19th International SPIN Workshop on Model Checking of Software (SPIN'12)
Reference:

pp. 234-240, Oxford, United Kingdoms, 2012
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Disjoint Sum of Product Minimization by Evolutionary Algorithms




Author:

Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
Workshop:
1st European Workshop on Hardware Optimisation Techniques (EvoHOT)
Reference:

Applications of Evolutionary Computing: EvoWorkshops 2004, LNCS 3005, p. 198-207, Coimbra, 2004
PDF:

[click here]



» An Approach to Formal Verification of Reconfigurable Systems




Author:

Görschwin Fey, Rolf Drechsler, Muazzam Ali
Workshop:
1st IFIP WG 10.5 Workshop on "Frontiers in Automotive Electronics"
Reference:

Darmstadt, 2003
PS:

[click here]



» Towards Generating Test Suites with High Functional Coverage for Error Effect Simulation




Author:

Aljoscha Windhorst, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems
Reference:

Amsterdam, The Netherlands, 2015
Hyperlink:

[Link to the Workshop]



» Improved Circuit-to-CNF Transformation for SAT-based ATPG




Author:

Daniel Tille, René Krenz-Bååth, Jürgen Schlöffel, Rolf Drechsler
Workshop:
20. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Reference:

Wien, 2008
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Parallelisierung von SAT-basierter Testmustergenerierung




Author:

Daniel Tille, Robert Wille, Rolf Drechsler
Workshop:
21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007)
Reference:

pp. 213-217, Hamburg, 2007
Hyperlink:

[Link to the Workshop]



» A Fast Untestability Proof for SAT-based ATPG




Author:

Daniel Tille, Rolf Drechsler
Workshop:
21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009
Reference:

Bremen, 2009
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Algorithms for ATPG under Leakage Constraints




Author:

Görschwin Fey
Workshop:
21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009
Reference:

Bremen, 2009
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» A Better-Than-Worst-Case Robustness Measure




Author:

Stefan Frehse, Görschwin Fey, Rolf Drechsler
Workshop:
22. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2010
Reference:

Paderborn, 2010
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization




Author:

Stephan Eggersglüß, Rolf Drechsler
Workshop:
23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011
Reference:

Passau, 2011
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Latency Analysis for Sequential Circuits




Author:

Alexander Finder, André Sülflow, Görschwin Fey
Workshop:
23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011
Reference:

Passau, 2011
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Automated Debugging from Pre-Silicon to Post-Silicon




Author:

Mehdi Dehbashi, Görschwin Fey
Workshop:
24. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Cottbus, Germany, 2012
Hyperlink:

[Link to the Workshop]



» Towards Debug Automation for Timing Bugs at RTL




Author:

Mehdi Dehbashi, Görschwin Fey
Workshop:
25. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Dresden, Germany, 2013
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms




Author:

Mehdi Dehbashi, Görschwin Fey
Workshop:
26. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Bad Staffelstein, Germany, 2014
Hyperlink:

[Link to the Workshop]



» Leichtgewichtige Datenkompressions-Architektur für IEEE 1149.1-kompatible Testschnittstellen




Author:

Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Workshop:
28. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Siegen, Germany, 2016
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» A Hybrid Algorithm to Conservatively Check the Robustness of Circuits




Author:

Niels Thole, Lorena Anghel, Görschwin Fey
Workshop:
28. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Siegen, Germany, 2016
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Eliminierung von energieunsicheren Tests in kompakten Testmengen




Author:

Stephan Eggersglüß
Workshop:
28. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Siegen, Germany, 2016
Hyperlink:

[Link to the Workshop]



» A Lightweight Method for Transient Test Power Pattern Analysis for Pattern Selection




Author:

Harshad Dhotre, Stephan Eggersglüß
Workshop:
29. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017)
Reference:

Lübeck, Germany, 2017
Hyperlink:

[Link to the Workshop]



» Revisiting Symbolic Software-implemented Fault Injection




Author:

Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop:
2nd International Workshop on Resiliency in Embedded Electronic Systems (REES)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Finding Compact BDDs Using Genetic Programming




Author:

Ulrich Kühne, Nicole Drechsler
Workshop:
3rd European Workshop on Evolutionary Computation in Hardware Optimisation (EvoHOT)
Reference:

LNCS 3907, pp. 308-319, Budapest, 2006
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion




Author:

Doina Logofatu, Rolf Drechsler
Workshop:
3rd European Workshop on Hardware Optimisation Techniques (EvoHOT)
Reference:

LNCS 3907, pp. 320-331, Budapest, 2006
Hyperlink:

[Link to the Workshop]



» A Human-Centered Approach to Routing for Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Andre Pols and Rolf Drechsler
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Computing Exact Fault Candidates Incrementally




Author:

Heinz Riener, Görschwin Fey
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Making Waveforms Great Again




Author:

Jannis Stoppe and Rolf Drechsler
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Mining Latency Guarantees for RT-level Designs




Author:

Jan Malburg, Heinz Riener, Görschwin Fey
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Verilog2GEXF - Dynamic Large Scale Circuit Visualization




Author:

Kenneth Schmitz, Jannis Stoppe, Rolf Drechsler
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Random Pattern Testability of Circuits Derived from BDDs




Author:

Junhao Shi, Göschwin Fey and Rolf Drechsler
Workshop:
4th Workshop on RTL and High Level Testing(WRTLT'03)
Reference:

p.70-78, Xi'an, 2003
PDF:

[click here]



» GAME-HDL: Implementation of Evolutionary Algorithms using Hardware Description Languages




Author:

Rolf Drechsler, Nicole Drechsler
Workshop:
5th European Workshop on Evolutionary Computation in Image Analysis and Signal Processing (EvoIASP2003)
Reference:

LNCS 2611, pp. 378-387, Colchester, 2003
PDF:

[click here]



» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
5th International Design & Test Workshop (IDT)
Reference:

pp. 143-148, Abu Dhabi, 2010
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» SAT-based ATPG for Reversible Circuits




Author:

Hongyan Zhang, Robert Wille, Rolf Drechsler
Workshop:
5th International Design & Test Workshop (IDT)
Reference:

pp. 149-154, Abu Dhabi, 2010
Hyperlink:

[Link to the Workshop]



» Debugging Sequential Circuits Using Boolean Satisfiability




Author:

Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith
Workshop:
5th International Workshop on Microprocessor Test and Verification (MTV'04)
Reference:

Austin, 2004



» Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method




Author:

Laurent Fribourg, Ulrich Kühne
Workshop:
5th Workshop on Reachability Problems (RP)
Reference:

Genua, 2011
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Improving ESOP-based Synthesis of Reversible Logic Using Evolutionary Algorithms




Author:

Rolf Drechsler, Alexander Finder, Robert Wille
Workshop:
6th European Workshop on Hardware Optimization Techniques (EvoHOT)
Reference:

Applications of Evolutionary Computation, LNCS 6625, pp. 151-161, Turin, 2011
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» HW/SW Co-Verification of a RISC CPU using Bounded Model Checking




Author:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop:
6th International Workshop on Microprocessor Test and Verification (MTV'05)
Reference:

pp. 133-137, Austin, 2005
PDF:

[click here]



» Towards Proving TLM Properties with Local Variables




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
7th International Workshop on Constraints in Formal Verification (CFV)
Reference:

San Jose, 2011
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Efficient Design-Flow for Counting Heads




Author:

Sebastian Kinder und Rolf Drechsler
Workshop:
8. Bieleschweig Workshop „Systems Engineering”: Modellbasierte Entwicklung & Human-Centered Engineering
Reference:

Braunschweig 2006
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Protocol Compliance Checking of SystemC TLM Models




Author:

Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Workshop:
8. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS)
Reference:

pp. 27-32, Bremen, 2011
Hyperlink:

[Link to the Workshop]



» Towards Automatic Scenario Generation from Coverage Information




Author:

Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Workshop:
8th International Workshop on Automation of Software Test (AST)
Reference:

pp. 82-88, San Francisco, 2013
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Building Free Binary Decision Diagrams Using SAT Solvers




Author:

Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop:
8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Reference:

Oslo, 2007
Hyperlink:

[Link to the Workshop]



» Estimating the Quality of AND-EXOR Optimization Results




Author:

Sebastian Kinder, Görschwin Fey and Rolf Drechsler
Workshop:
8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Reference:

Oslo, 2007
Hyperlink:

[Link to the Workshop]



» Design Understanding by Feature Localization on ESL




Author:

Marc Michael, Daniel Große, Rolf Drechsler
Workshop:
9. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS)
Reference:

pp. 19-24, Dresden, 2012
Hyperlink:

[Link to the Workshop]



» Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow




Author:

Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop:
9th International Workshop on Microprocessor Test and Verification (MTV)
Reference:

pp. 88-93, Austin, Texas, 2008
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» False Noise Analysis Using Branch & Bound and SAT




Author:

Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
Workshop:
ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2008)
Reference:

Monterey, 2008
Hyperlink:

[Link to the Workshop]



» SMT-Based CPS Parameter Synthesis




Author:

Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem
Workshop:
Applied Verification for Continuous and Hybrid Systems (ARCH@CPSWeek'16)
Reference:

pp. 126-133, Vienna, Austria, 2016
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Bounded Model Checking mit SystemC




Author:

Sebastian Kinder, Rolf Drechsler, Jan Peleska
Workshop:
Bieleschweig 6 - Workshop "Systems Engineering"
Reference:

Braunschweig, 2005



» Robustness Check for Multiple Faults using Formal Techniques




Author:

Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop:
Constraints in Formal Verification (CFV)
Reference:

Grenoble, France, 2009
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques (Extended Abstract)




Author:

Jan Malburg, Niklas Krafczyk, Görschwin Fey
Workshop:
DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Reference:

page 30, Dresden, Germany, 2014
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Mutation based Feature Localization




Author:

Jan Malburg, Emmanuelle Encrenaz-Tiphene, Görschwin Fey
Workshop:
DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Reference:

pp. 55-60, Dresden, Germany, 2014
Hyperlink:

[Link to the Workshop]



» Towards a Multi-dimensional and Dynamic Visualization for ESL Designs




Author:

Jannis Stoppe, Marc Michael, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Reference:

Dresden, Germany, 2014
Hyperlink:

[Link to the Workshop]



» Ecore Model Generation from SystemC/C++ Implementations




Author:

Jannis Stoppe, Rolf Drechsler
Workshop:
DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Workshop]



» Matching Abstract and Concrete Hardware Models for Design Understanding




Author:

Tino Flenker, Görschwin Fey
Workshop:
DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Towards analysing feature locations through testing traces with BUT4Reuse




Author:

Jabier Martinez, Jan Malburg, Tewfik Ziadi, Görschwin Fey
Workshop:
DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Workshop]



» SystemC-based ESL Verification Flow Integrating Property Checking and Automatic Debugging




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
DATE Friday Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design
Reference:

Dresden, 2012
Hyperlink:

[Link to the Workshop]



» metaSMT: Focus on Your Application not on Solver Integration




Author:

Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler
Workshop:
DIFTS'11: 1st International workshop on design and implementation of formal tools and systems
Reference:

pp. 22-29, Austin, USA, 2011
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Contradiction Analysis for Constraint-based Random Simulation




Author:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Workshop:
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Reference:

pp. 25-30, Dresden, 2008
Hyperlink:

[Link to the Workshop]



» Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs




Author:

Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Workshop:
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Reference:

Dresden, 2008
Hyperlink:

[Link to the Workshop]



» Compilation of Methodologies to Speed up the Verification Process at System Level




Author:

Stephan Radke, Steffen Rülke, Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, Simon Hufnagel, Nico Bannow, Helmut Brazdrum, Peter Janssen, Hoang M. Le, Daniel Große, Rolf Drechsler, Erhard Fehlauer, Gernot Koch, Andreas Burger, Oliver Bringmann, Wolfgang Rosenstiel, Finn Haedicke, Ralph Görgen, Jan-Hendrik Oetjens
Workshop:
edaWorkshop
Reference:

pp. 57-62, Hannover, 2012
Hyperlink:

[Link to the Workshop]



» Formale Modellextraktion von SystemC Entwürfen




Author:

Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
Workshop:
edaWorkshop
Reference:

pp. 7-12, Hannover 2008
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Functional Analysis of Circuits Under Timing Variations




Author:

Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Workshop:
edaWorkshop
Reference:

Hannover, Germany, 2012
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache




Author:

Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Workshop:
edaWorkshop
Reference:

pp. 53-58, Dresden, 2013
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern




Author:

Rolf Drechsler, Görschwin Fey, Jürgen Schlöffel
Workshop:
edaWorkshop 2007
Reference:

Hannover, 2007
Hyperlink:

[Link to the Workshop]



» Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors




Author:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop:
Entwurfsmethoden für Nanometer VLSI Design
Reference:

pp. 308-312, Bonn, 2005
PDF:

[click here]



» Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking




Author:

Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop:
Fifth IEEE Dallas Circuits and Systems Workshop
Reference:

pp. 147-150, Dallas, 2006
Hyperlink:

[Link to the Workshop]



» Exact Toffoli Network Synthesis of Reversible Logic using Boolean Satisfiability




Author:

Daniel Große, Xiaobo Chen, Rolf Drechsler
Workshop:
Fifth IEEE Dallas Circuits and Systems Workshop
Reference:

pp. 51-54, Dallas, 2006
Hyperlink:

[Link to the Workshop]



» Model-Based Diagnosis for Programmable Logic Controllers




Author:

Andre Sülflow, Rolf Drechsler
Workshop:
Gemeinsamer Workshop der Informatik-Graduiertenkollegs und Forschungskollegs
Reference:

Dagstuhl, 2009



» Synthesizing Checkers for On-line Verification of System-on-Chip Designs




Author:

Rolf Drechsler
Workshop:
GI/GMM/ITG Fachtagung Entwurf Integrierter Schaltungen (11. E.I.S.-Workshop)
Reference:

Erlangen, 2003, page 69



» Analyzing an SET at Gate Level using a Conservative Approach




Author:

Niels Thole, Görschwin Fey, Alberto Garcia-Ortiz
Workshop:
GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Bad Urach, 2015
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Erzeugung diagnostischer Testmuster unter komplexen Constraints




Author:

Tobias Koal, Stephan Eggersglüß, Mario Schölzel
Workshop:
GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Bad Urach, 2015
Hyperlink:

[Link to the Workshop]



» Fehlereffektsimulation mittels virtueller Prototypen




Author:

Sebastian Reiter, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Rolf Drechsler, Wolfgang Ecker, Thomas Kruse, Christoph Kuznik, Jo Laufenberg, Hoang M. Le, Petra Maier, Daniel Müller-Gritschneder, Hendrik Post, Jan-Hendrik Oetjens, Wolfgang Rosenstiel, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Workshop:
GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Bad Urach, 2015
Hyperlink:

[Link to the Workshop]



» Implementation and Visualization of a BDD Package in JAVA




Author:

Rolf Drechsler, Jochen Römmler
Workshop:
GI/ITG/GMM-Workshop 2002, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

Tübingen, 2002, pages 219 - 228
PDF:

[click here]
PS:

[click here]



» A Tight Lower Bound for Dynamic BDD Minimization




Author:

Rüdiger Ebendt, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

pp. 233-242, Kaiserslautern, 2004
PS:

[click here]



» Acceleration of SAT-based Iterative Property Checking




Author:

Daniel Große, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

München, 2005
PDF:

[click here]



» Cost-efficient Formal Block Verification for ASIC Design




Author:

K. Winkelmann, J. Trylus, D. Stoffel, Görschwin Fey
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

Bremen, 2003, pages 184-188
PDF:

[click here]



» Efficient (Non-)Reachability Analysis of Counterexamples




Author:

Rolf Drechsler, Wolfgang Günther, Burkhard Stubert
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

pp. 250-259, Kaiserslautern, 2004
PDF:

[click here]



» Formal Verification on the Word Level using SAT-like Proof Techniques




Author:

Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

pp. 165-173, Erlangen, 2007
Hyperlink:

[Link to the Workshop]



» Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen




Author:

Daniel Große, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

pp. 229-238, Bremen, 2003
PDF:

[click here]



» Modellierung eines Mikroprozessors in SystemC




Author:

Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

München, 2005
PDF:

[click here]



» SAT-Based Calculation of Source Code Coverage for BMC




Author:

Görschwin Fey, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

Dresden, 2006
PDF:

[click here]



» Symbolic Simulation of Algorithms Specified in HDL




Author:

Klaus-Jürgen Englert, Bernd Becker, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

Tübingen, 2002, pages 113 - 122
PDF:

[click here]
PS:

[click here]



» Technische Dokumentation von Soft- und Hardware-Systemen: Die vergessene Welt




Author:

Beate Muranko, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

Dresden, 2006
PDF:

[click here]



» Using Synthesis Techniques in SAT Solvers




Author:

Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

pp. 165-173, Kaiserslautern, 2004
PDF:

[click here]



» Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse




Author:

Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

pp. 101-110, Erlangen, 2007
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints




Author:

Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler
Workshop:
IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)
Reference:

Niigata, Japan, 2012
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Using Optimization Techniques to Increase Test Compaction




Author:

Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Workshop:
IEEE 14th Workshop on RTL and High Level Testing (WRTLT'13)
Reference:

Yilan, Taiwan, 2013
Hyperlink:

[Link to the Workshop]



» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits




Author:

Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler
Workshop:
IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
Reference:

pp. 31-36, Beijing, P.R.China, 2007
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Experimental Studies on SMT-based Debugging




Author:

Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop:
IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08)
Reference:

pp. 93-98, Japan, 2008
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» On Timing-Aware ATPG using Pseudo-Boolean Optimization




Author:

Stephan Eggersglüß, Rolf Drechsler
Workshop:
IEEE European Test Symposium (ETS), Informal Digest of Papers
Reference:

Trondheim, 2011
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop:
IEEE European Test Symposium (ETS), Informal Digest of Papers
Reference:

Lago Maggiore, 2008
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» SAT-based ATPG for Path Delay Fault in Industrial Circuits




Author:

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Workshop:
IEEE European Test Symposium (ETS), Informal Digest of Papers
Reference:

Freiburg, 2007
Hyperlink:

[Link to the Workshop]



» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability




Author:

Junhao Shi, Görschwin Fey and Rolf Drechsler
Workshop:
IEEE European Test Workshop (ETW'03)
Reference:

pp. 109-110, Maastricht, 2003
PDF:

[click here]



» Test Case Generation from Mutants using Model Checking Techniques




Author:

Heinz Riener, Roderick Bloem, Görschwin Fey
Workshop:
IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops (ICSTW'11)
Reference:

pp 388 - 397, Berlin, Germany, 2011
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» BDD-Based Verification of Scalable Designs




Author:

Daniel Große, Rolf Drechsler
Workshop:
IEEE International High Level Design Validation and Test Workshop (HLDVT'2003)
Reference:

pp. 123-128, San Francisco, 2003
PDF:

[click here]



» Behavior Driven Development for Circuit Design and Verification




Author:

Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Workshop:
IEEE International Workshop on High-Level Design Validation and Test (HLDVT)
Reference:

pp. 9-16, Huntington Beach, USA, 2012
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Towards Analyzing Functional Coverage in SystemC TLM Property Checking




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
IEEE International Workshop on High-Level Design Validation and Test (HLDVT)
Reference:

pp. 67-74, Anaheim, 2010
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Formal Analysis Techniques: A Basis for High-Quality Designs




Author:

Stephan Eggersglüß, Rolf Drechsler
Workshop:
IEEE International Workshop on Processor Verification, Test and Debug
Reference:

Invited Talk, Trondheim, 2011
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Targeting Leakage Constraints during ATPG




Author:

Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Workshop:
IEEE International Workshop on Silicon Debug and Diagnosis
Reference:

San Diego, 2008
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Efficient Hierarchical System Debugging for Property Checking




Author:

Görschwin Fey, Rolf Drechsler
Workshop:
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Sopron, 2005
PDF:

[click here]



» PASSAT: Efficient SAT-based Test Pattern Generation




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop:
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Sopron, 2005
PS:

[click here]



» Computing Bounds for Fault Tolerance using Formal Techniques




Author:

Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Workshop:
IEEE Workshop on Design for Reliability and Variability (DRV)
Reference:

Santa Clara, USA, 2008
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-Micron Interconnects.




Author:

Tudor Murgan, Petru Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
Workshop:
In Intl. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sept. 2007.
Reference:

pp. 242-254, Göteborg, Sweden
Hyperlink:

[Link to the Workshop]



» Counterexample-Guided Diagnosis




Author:

Heinz Riener, Görschwin Fey
Workshop:
International Verification and Security Workshop (IVSW'16)
Reference:

Sant Feliu de Guixols, Catalunya, Spain, 2016
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Generating good properties from a small number of use cases




Author:

Jan Malburg, Tino Flenker, Görschwin Fey
Workshop:
International Verification and Security Workshop (IVSW'16)
Reference:

Sant Feliu de Guixols, Catalunya, Spain, 2016
Hyperlink:

[Link to the Workshop]



» Evaluating Debugging Algorithms from a Qualitative Perspective




Author:

Alexander Finder, Görschwin Fey
Workshop:
International Workshop on Boolean Problems
Reference:

Freiberg, 2010
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment




Author:

Rolf Drechsler, Stefan Höreth
Workshop:
International Workshop on Boolean Problems
Reference:

Freiberg, 2002, pages 195-200
PDF:

[click here]



» Minimizing the Number of Paths in BDDs




Author:

Görschwin Fey, Rolf Derchsler
Workshop:
International Workshop on Boolean Problems
Reference:

Freiberg, 2002, pages 149 - 156
PDF:

[click here]
PS:

[click here]



» On the computational complexity of error metrics in approximate computing




Author:

Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Reference:

Freiberg, Germany, 2016
Hyperlink:

[Link to the Workshop]



» Reversible Logic Synthesis with Output Permutation




Author:

Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Reference:

Freiberg, 2008
Hyperlink:

[Link to the Workshop]



» Towards Embedding of Large Functions for Reversible Logic




Author:

Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Reference:

Freiberg, 2012
Hyperlink:

[Link to the Workshop]



» Experimental Studies on Test Pattern Generation for BDD Circuits




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems (IWSBP)
Reference:

pp. 71-76, Freiberg, 2004
PDF:

[click here]



» Using QBF to Increase the Accuracy of SAT-Based Debugging




Author:

Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop:
International Workshop on Constraints in Formal Verification (CFV)
Reference:

Grenoble, France, 2009
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Coverage at the Formal Specification Level




Author:

Rolf Drechsler, Julia Seiter, Mathias Soeken
Workshop:
International Workshop on Design and Implementation of Formal Tools and Systems (DIFTS)
Reference:

Lausanne, Switzerland, 2014
Hyperlink:

[Link to the Workshop]



» SystemCDG - AI Based Coverage Driven Stimuli Generation for SystemC




Author:

Jannis Stoppe, Arved Friedemann, Rolf Drechsler
Workshop:
International Workshop on Logic & Synthesis (IWLS)
Reference:

Austin, TX, USA, 2016
Hyperlink:

[Link to the Workshop]



» On the Exact Minimization of Path-Related Objective Functions for BDDs




Author:

Rüdiger Ebendt, Rolf Drechsler
Workshop:
International Workshop on Logic and Synthesis (IWLS'05)
Reference:

pp. 333-400, Lake Arrowhead, California, 2005
PDF:

[click here]



» Low Power Optimization Technique for BDD Mapped Finite State Machines




Author:

M. Kerttu, P. Lindgren, Rolf Drechsler, M. Thornton
Workshop:
International Workshop on Logic Synthesis (IWLS'2002)
Reference:

New Orleans, 2002



» Reducing Reversible Circuit Cost by Adding Lines




Author:

D. Michael Miller, Robert Wille, Rolf Drechsler
Workshop:
International Workshop on Logic Synthesis (IWLS)
Reference:

Berkeley, 2009
Hyperlink:

[Link to the Workshop]



» Simulation Graphs for Reverse Engineering




Author:

Baruch Sterin, Mathias Soeken, Rolf Drechsler, Robert K. Brayton
Workshop:
International Workshop on Logic Synthesis (IWLS)
Reference:

Mountain View, CA, USA, 2015
Hyperlink:

[Link to the Workshop]



» Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost




Author:

Robert Wille, Mehdi Saeedi, Rolf Drechsler
Workshop:
International Workshop on Logic Synthesis (IWLS)
Reference:

Berkeley, 2009
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» SyReC: A Programming Language for Synthesis of Reversible Circuits




Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop:
International Workshop on Logic Synthesis (IWLS)
Reference:

Irvine, 2010
Hyperlink:

[Link to the Workshop]



» Verification of Embedded Systems Using Modeling and Implementation Languages




Author:

Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop:
International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12)
Reference:

pp. 67-72, Tampere, Finland, 2012
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Game-based Synthesis of Distributed Controllers for Sampled Switched Systems




Author:

Laurent Fribourg, Ulrich Kühne, Nicolas Markey
Workshop:
International Workshop on Synthesis of Complex Parameters
Reference:

London, 2015
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Model-Based Diagnosis versus Error Explanation




Author:

Heinz Riener, Görschwin Fey
Workshop:
International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES'12) in conjunction with 49th Design Automation Conference (DAC'12)
Reference:

San Francisco, USA, 2012
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation




Author:

Rolf Drechsler, M. Kerttu, P. Lindgren, M. Thornton
Workshop:
International Workshop on System-on-Chip for Real-Time Applications 2002
Reference:

Banff, 2002



» Law-based Verification for Complex Swarm Systems




Author:

Rolf Drechsler, Hoang M. Le, Mathias Soeken, Robert Wille
Workshop:
International Workshop on the Swarm at the Edge of the Cloud
Reference:

Montreal, Canada
Hyperlink:

[Link to the Workshop]



» Counterexample-Guided EF Synthesis of Boolean Functions




Author:

Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference:

Bremen, Germany, 2017
Hyperlink:

[Link to the Workshop]



» Der Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips




Author:

Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference:

Bremen, Germany, 2017
Hyperlink:

[Link to the Workshop]



» Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing




Author:

Saman Fröhlich, Daniel Große, Rolf Drechsler
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference:

Bremen, Germany, 2017
Hyperlink:

[Link to the Workshop]



» Towards a Base Model for UML and OCL Verification




Author:

Frank Hilken, Philipp Niemann, Robert Wille, Martin Gogolla
Workshop:
Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference:

Valencia, Spain, 2014
Hyperlink:

[Link to the Workshop]



» Towards Automatic Determination of Problem Bounds for Object Instantiation in Static Model Verification




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Model-Driven Engineering, Verification, And Validation (MoDeVVa)
Reference:

Wellington, 2011
Hyperlink:

[Link to the Workshop]



» Quo Vadis, Reversible Circuit Design? Towards Scaling Design and Synthesis of Reversible Circuits




Author:

Eleonora Schönborn, Robert Wille, Rolf Drechsler
Workshop:
Reed-Muller Workshop
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Workshop]



» Self-Inverse Functions and Palindromic Circuits




Author:

Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
Workshop:
Reed-Muller Workshop
Reference:

Waterloo, Canada, 2015, pre-print available at arXiv:1502.05825
Hyperlink:

[Link to the Workshop]



» Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques




Author:

D. Michael Miller, Gerhard W. Dueck, Robert Wille
Workshop:
Reed-Muller Workshop
Reference:

Naha, Okinawa, 2009
Hyperlink:

[Link to the Workshop]



» Synthesizing Reversible Logic: An Overview




Author:

Robert Wille, Rolf Drechsler
Workshop:
Reed-Muller Workshop
Reference:

Naha, Okinawa, 2009
Hyperlink:

[Link to the Workshop]



» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic




Author:

Robert Wille, Rolf Drechsler
Workshop:
Reversible Computation
Reference:

York, 2009
Hyperlink:

[Link to the Workshop]



» A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop:
Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009
Reference:

Sevilla, Spain, 2009
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Extraktion von Frame Conditions aus Operation Contracts




Author:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Workshop:
Software Engineering (SE)
Reference:

Vienna, Austria, 2016
Hyperlink:

[Link to the Workshop]



» Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines




Author:

Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
Workshop:
SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems
Reference:

pp. 181-188, Newport Beach, 2011
Hyperlink:

[Link to the Workshop]



» Tangicons - Programmieren im Kindergarten




Author:

Thomas Winkler, Florian Scharf, Judith Peters, Michael Herczeg
Workshop:
Tagung Mensch & Computer
Reference:

pp. 23-24, Chemnitz, 2011
Hyperlink:

[Link to the Workshop]



» Synthesis of Optical Circuits with Contradictory Optimization Objectives




Author:

Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Workshop:
The 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Workshop]



» RobuCheck: A Robustness Checker for Digital Circuits




Author:

Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Workshop:
The First International Workshop on Dynamic Aspects in Dependability Models for Fault-Tolerant Systems (DYADEM-FTS)
Reference:

Valencia, 2010
Hyperlink:

[Link to the Workshop]



» Bounded Model Checking of Tram Control Systems




Author:

Sebastian Kinder, Daniel Große, Jan Peleska, Rolf Drechsler
Workshop:
TRain Workshop @ SEFM2005
Reference:

Koblenz, 2005



» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern




Author:

Rolf Drechsler
Workshop:
Treffen der ASIM/GI-Fachgruppen "Simulation technischer Systeme" und "Grundlagen und Methoden in Modellbildung und Simulation"
Reference:

Bremen, 2007
Hyperlink:

[Link to the Workshop]



» Visualized SystemC Debugging




Author:

Christian Genz, Frank Rogin, Rolf Drechsler, Steffen Rülke
Workshop:
University Booth at Design, Automation and Test in Europe (DATE07)
Reference:

Nizza, 2007
PDF:

[click here]



» FormED: A Formal Environment for Debugging




Author:

Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler
Workshop:
University Booth at Design, Automation and Test in Europe (DATE09)
Reference:

Nizza, 2009
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» VisSAT: Visualization of SAT Solver Internals




Author:

Robert Wille, Andre Sülflow, Christian Genz, Rolf Drechsler
Workshop:
University Booth at Design, Automation and Test in Europe (DATE10)
Reference:

Dresden, 2010
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture




Author:

Gökçe Aydos, Görschwin Fey
Workshop:
Workshop Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen
Reference:

Cottbus, Germany, 2015
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Using Lightweight Containers in Hardware/Software Co-Design for Security




Author:

Daniel Große, Kenneth Schmitz, Rolf Drechsler
Workshop:
Workshop on Computer-Aided Design and Implementation for Cryptography and Security (CADICS)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Workshop]



» Formal Robustness Checking




Author:

Görschwin Fey, Rolf Drechsler
Workshop:
Workshop on Constraints in Formal Verification, 2007
Reference:

Bremen, 2007
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Change Management for Hardware Designers




Author:

Martin Ring, Jannis Stoppe, Christoph Lüth, Rolf Drechsler
Workshop:
Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Workshop]



» Visualizing Microfluidic Biochips Interactively




Author:

Jannis Stoppe, Oliver Keszöcze, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Workshop]



» Integrating an SMT-based Model Finder into USE




Author:

Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler
Workshop:
Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference:

Saint-Malo, France, 2016
Hyperlink:

[Link to the Workshop]



» Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses




Author:

Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference:

Ottawa, Canada, 2015
Hyperlink:

[Link to the Workshop]



» lips: An IDE for Model Driven Engineering Based on Natural Language Processing




Author:

Oliver Keszöcze, Mathias Soeken, Eugen Kuksa, Rolf Drechsler
Workshop:
Workshop on Natural Language Analysis in Software Engineering (NaturaLiSE)
Reference:

pp. 31—38, San Francisco, 2013
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Customized Design Flows for Reversible Circuits Using RevKit




Author:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

pp. 91-96, Gent, 2011
Hyperlink:

[Link to the Workshop]



» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

pp. 55-58, Bremen, 2010
Hyperlink:

[Link to the Workshop]



» Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams




Author:

Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

Kopenhagen, 2012
Hyperlink:

[Link to the Workshop]



» RevKit: A Toolkit for Reversible Circuit Design




Author:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

pp. 69-72, Bremen, 2010
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Synthesis of Reversible Circuits with Minimal Lines for Large Functions




Author:

Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

pp. 59-70, Gent, 2011
Hyperlink:

[Link to the Workshop]



» Using πDDs in the Design for Reversible Circuits




Author:

Mathias Soeken, Robert Wille, Shin-Ichi Minato, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

Kopenhagen, 2012
Hyperlink:

[Link to the Workshop]



» Hohe Testmengenkompaktierung durch formale Optimierungstechniken




Author:

Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Workshop:
Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference:

Bad Staffelstein, 2014
Hyperlink:

[Link to the Workshop]



» Complete BDDs for Fast and Efficient Equivalence Checking, In Workshop on Computational Intelligence and Information Technologies




Author:

Rolf Drechsler
Workshop:
XXXVII International Scientific Conference on Information Communication and Energy Systems and Technologies (ICEST 2002)
Reference:

Nis, 2002, pages 741-744





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