Homepage Sitemap Contact




Home « Publications « Conferences

sort: [ Title ] [ Author ] [ Conferences ] [ Reference ]
search:





» Complete and Effective Robustness Checking by Means of Interpolation




Author:

Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler
Conference:
Formal Methods in Computer-Aided Design (FMCAD'12)
Reference:

Cambridge, UK, 2012, page 82-90
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits




Author:

Aaron Lye, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library




Author:

Abhoy Kole, Kamalika Datta, Indranil Sengupta and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Gran Canaria, Spain, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits




Author:

Abhoy Kole, Kamalika Datta, Indranil Sengupta, Robert Wille
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates




Author:

Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Augmenting All Solution SAT Solving for Circuits with Structural Information




Author:

Abraham Temesgen Tibebu, Görschwin Fey
Conference:
21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Budapest, Hungary, 2018
Hyperlink:

[Link to the Conference]



» Latency Analysis for Sequential Circuits




Author:

Alexander Finder, André Sülflow, Görschwin Fey
Conference:
16th IEEE European Test Symposium (ETS)
Reference:

pp. 129-134, Trondheim, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluating Debugging Algorithms from a Qualitative Perspective




Author:

Alexander Finder, Görschwin Fey
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 37-42, Southampton, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications




Author:

Alexander Finder, Jan-Philipp Witte, Görschwin Fey
Conference:
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Karlovy Vary, Czech Republic, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions




Author:

Alexander Finder, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 150-155, Barcelona, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the problems of realizing reliable and efficient ring oscillator PUFs on FPGAs.




Author:

Alexander Wild, Georg T. Becker, Tim Güneysu
Conference:
Hardware-Oriented Security and Trust (HOST) 2016: 103-108
Reference:

http://dx.doi.org/10.1109/HST.2016.7495565



» Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability




Author:

Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, USA, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Formal Verification of Optimized and Industrial Multipliers




Author:

Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Grenoble, France, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers




Author:

Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 351-356, Hong Kong SAR, China, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» PolyCleaner: Clean your Polynomials before Backward Rewriting to Verify Million-gate Multipliers




Author:

Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

San Diego, USA, 2018
Best Paper Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers




Author:

Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

Las Vegas, USA, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Late Breaking Results: Polynomial Formal Verification of Fast Adders




Author:

Alireza Mahzoon, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, USA, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Polynomial Formal Verification of Prefix Adders




Author:

Alireza Mahzoon, Rolf Drechsler
Conference:
Asian Test Symposium (ATS)
Reference:

Virtual Conference, Japan, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Accuracy and Compactness in Decision Diagrams for Quantum Computation




Author:

Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Florence, Italy, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits




Author:

Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
Conference:
49th IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Fredericton, NB, Canada, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking Using Gröbner Bases




Author:

Amr Sayed Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference:
Formal Methods in Computer Aided Design (FMCAD)
Reference:

Mountain View, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction




Author:

Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verification of the Decimal Floating-Point Square Root Operation,




Author:

Amr Sayed Ahmed, Hossam Fahmy, Ulrich Kühne
Conference:
19th IEEE European Test Symposium,
Reference:

Paderborn, Germany, 2014.
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits




Author:

Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015).
Reference:

pp. 1-6, Montpellier, France, 2015.
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Increasing the Accuracy of SAT-based Debugging




Author:

Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1326-1332, Nice, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Using Unsatisfiable Cores to Debug Multiple Design Errors




Author:

Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Conference:
IEEE Great Lakes Symposium on VLSI (GLSVLSI'08)
Reference:

pp. 77-82, Orlando, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Using QBF to Increase Accuracy of SAT-Based Debugging




Author:

Andre Sülflow, Görschwin Fey, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

pp.641-644, Paris, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Robust Multi-Objective Optimization in High Dimensional Spaces




Author:

André Sülflow, Nicole Drechsler, Rolf Drechsler
Conference:
Fourth International Conference on Evolutionary Multi-Criterion Optimization
Reference:

pp. 715-726, Matsushima, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluation of Cardinality Constraints on SMT-based Debugging




Author:

Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
Conference:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 298-303, Naha, Okinawa, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Fault Localization for Programmable Logic Controllers




Author:

Andre Sülflow, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT)
Reference:

pp. 247-256, Braunschweig, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC




Author:

Andre Sülflow, Rolf Drechsler
Conference:
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Reference:

pp. 42, Oslo, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verification of PLC Programs using Formal Proof Techniques




Author:

Andre Sülflow, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
Reference:

pp. 43-50, Budapest, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen




Author:

Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler
Conference:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Reference:

pp. 45-52, Stuttgart, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» WoLFram - A Word Level Framework for Formal Verification




Author:

Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
Conference:
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Reference:

pp. 11-17, Paris, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Constraint-based Platform Variants Specification for Early System Verification




Author:

Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, Wolgang Rosenstiel
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 800-805, Singapore, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm




Author:

Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
50th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Miyazaki, Japan, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improved Look-ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits




Author:

Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler and Hafizur Rahaman
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Florida, USA, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits




Author:

Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Hong Kong SAR, China, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Minimization of Fully Testable 2-SPP Networks




Author:

Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1300-1305, Munich, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure




Author:

Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 182-195, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Dedicated Synthesis for MZI-based Optical Circuits based on AND-Inverter Graphs




Author:

Arighna Deb, Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Irvine, USA, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» OR-Inverter Graphs for the Synthesis of Optical Circuits




Author:

Arighna Deb, Robert Wille, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[Link to the Conference]



» An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization




Author:

Arighna Deb, Robert Wille, Rolf Drechsler, Debesh Das
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Requirement Phrasing Assistance using Automatic Quality Assessment




Author:

Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Reference:

Belgrade, Serbia, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits




Author:

Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking




Author:

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» ProACt: A Processor for High Performance On-demand Approximate Computing




Author:

Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Conference:
27th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 463-466, Banff, Alberta, Canada, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Yise - A novel Framework for Boolean Networks using Y-Inverter Graphs




Author:

Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Conference:
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

pp. 114-117, Vienna, Austria, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Ensuring Safety and Reliability of IP-based System Design – A Container Approach




Author:

Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
Conference:
IEEE International Symposium on Rapid System Protoyping (RSP), 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Approximation-aware Rewriting of AIGs for Error Tolerant Applications




Author:

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Approximation-aware Testing for Approximate Circuits




Author:

Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
Conference:
23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 239 - 244, Jeju, Korea, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Technical Documentation of Software and Hardware in Embedded Systems




Author:

Beate Muranko, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2006)
Reference:

Nice, France 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Recent Advances in SAT-based ATPG: Non-Standard Fault Models, Multi Constraints and Optimization




Author:

Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
Conference:
International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Reference:

pp. 1-10, Santorini, Greece, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SAT-Lancer: A Hardware SAT-Solver for Self-Verification




Author:

Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler
Conference:
28th ACM Great Lakes Symposium on VLSI (GLVLSI)
Reference:

pp. 479-482, Chicago, Illinois, USA, 2018
Received Best Poster Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SAT-Hard: A Learning-based Hardware SAT-Solver




Author:

Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große and Rolf Drechsler
Conference:
EUROMICRO Digital System Design Conference (DSD)
Reference:

Kallithea - Chalkidiki, Greece, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Cube Pairing Approach for Synthesis of ESOP based Reversible Circuit




Author:

Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler
Conference:
44rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Bremen, 2014
Hyperlink:

[Link to the Conference]



» Post Synthesis-Optimization of Reversible Circuit using Template Matching




Author:

Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
In 2020 24th International Symposium on VLSI Design and Test (VDAT)
Reference:

pp. 1-4. IEEE, 2020, DOI: 10.1109/VDAT50263.2020.9190279
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Overcoming Limitations of the SystemC Data Introspection




Author:

Christian Genz, Rolf Drechsler
Conference:
Design Automation and Test in Europe (DATE)
Reference:

pp. 590-593, Nice, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» System Exploration of SystemC Designs




Author:

Christian Genz, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 335-340, Karlsruhe, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Visualization of SystemC Designs




Author:

Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

pp. 413-416, New Orleans, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Modeling for Explainability: Ethical Decision-Making in Automated Resource Allocation




Author:

Christina Cociancig, Christoph Lüth, Rolf Drechsler
Conference:
Upper-Rhine Artificial Intelligence Symposium (UR-AI 2021)
Reference:

Kaiserslautern, Germany, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Choosing the right technique for the right restriction - a domain-specific approach for enforcing search-space restrictions in evolutionary algorithms




Author:

Christina Plump, Bernhard Berger, Rolf Drechsler
Conference:
LDIC-2022
Reference:

Bremen, Germany
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Adapting mutation and recombination operators to range-aware relations in real-world application data




Author:

Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference:
The Genetic and Evolutionary Computation Conference (GECCO Companion)
Reference:

Boston, USA, 2022
Hyperlink:

[Link to the Conference]



» Domain-driven correlation-aware recombination and mutation operators for complex real-world applications




Author:

Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference:
IEEE Congress on Evolutionary Computation (CEC)
Reference:

Kraków, Poland, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving evolutionary algorithms by enhancing an approximative fitness function through prediction intervals




Author:

Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference:
IEEE Congress on Evolutionary Computation (CEC)
Reference:

Krakow, Poland, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Using density of training data to improve evolutionary algorithms with approximative fitness functions




Author:

Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference:
Congress of Evolutionary Computation (CEC)
Reference:

Padua, Italien, 2022
Hyperlink:

[Link to the Conference]



» A Unified Formulation of Behavioral Semantics for SysML Models




Author:

Christoph Hilken, Jan Peleska, Robert Wille
Conference:
International Conference on Model-Driven Engineering and Software Development
Reference:

Angers, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts




Author:

Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization




Author:

Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe Conference (DATE)
Reference:

Grenoble, France, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Secure and Private, yet Lightweight, Authentication for the IoT via PUF and CBKA




Author:

Christopher Huth, Aydin Aysu, Jorge Guajardo, Paul Duplys, Tim Güneysu
Conference:
ICISC 2016: 28-48
Reference:

http://dx.doi.org/10.1007/978-3-319-53177-9_2



» Secure software update and IP protection for untrusted devices in the Internet of Things via physically unclonable functions




Author:

Christopher Huth, Paul Duplys, Tim Güneysu
Conference:
IEEE International Conference on Pervasive Computing and Communication Workshops (PerCom Workshops)
Reference:

pages 1-6, Sydney, Australia
Hyperlink:

[Link to the Conference]



» On the Energy Cost of Channel Based Key Agreement




Author:

Christopher Huth, René Guillaume, Paul Duplys, Kumaragurubaran Velmurugan, Tim Güneysu
Conference:
TrustED@CCS 2016: 31-41
Reference:

http://doi.acm.org/10.1145/2995289.2995291



» ML-based Power Estimation of Convolutional Neural Networks on GPGPUs




Author:

Christopher Metz, Mehran Goli, Rolf Drechsler
Conference:
25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Prague, Czech Republic, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Work-in-Progress: Early Power Estimation of CUDA-based CNNs on GPGPUs




Author:

Christopher Metz, Mehran Goli, Rolf Drechsler
Conference:
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Reference:

VIRTUAL CONFERENCE, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Mapping NCV Circuits to Optimized Clifford+T Circuits




Author:

D. Michael Miller, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesizing Reversible Circuits for Irreversible Functions




Author:

D. Michael Miller, Robert Wille, Gerhard W. Dueck
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 749-756, Patras, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reducing Reversible Circuit Cost by Adding Lines




Author:

D. Michael Miller, Robert Wille, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 217-222, Barcelona, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates




Author:

D. Michael Miller, Robert Wille, Z. Sasanian
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 288-293, Tuusula, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Modeling Multi-Valued Circuits in SystemC




Author:

Daniel Große, Görschwin Fey and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference:

pp. 281-286, Tokyo, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues




Author:

Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 146-151, Barcelona, 2007
Received Best Paper Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Guided Lightweight Software Test Qualification for IP Integration using Virtual Prototypes




Author:

Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler
Conference:
IEEE International Conference on Computer Design (ICCD)
Reference:

Phoenix, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Proving Transaction and System-level Properties of Untimed SystemC TLM Designs




Author:

Daniel Große, Hoang M. Le, Rolf Drechsler
Conference:
International Conference on Formal Methods and Models for Codesign (MEMOCODE)
Reference:

pp. 113-122, Grenoble, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction




Author:

Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 223-228, Lausanne, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares




Author:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Contradiction Analysis for Constraint-based Random Simulation




Author:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 130-135, Stuttgart, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Contradictory Antecedent Debugging in Bounded Model Checking




Author:

Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 173-176, Boston, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Acceleration of SAT-based Iterative Property Checking




Author:

Daniel Große, Rolf Drechsler
Conference:
Correct Hardware Design and Verification Methods (CHARME)
Reference:

pp. 349-353, Saarbrücken, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Checkers for SystemC Designs




Author:

Daniel Große, Rolf Drechsler
Conference:
Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004)
Reference:

pp. 171-178, San Diego, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» CheckSyC: An Efficient Property Checker for RTL SystemC Designs




Author:

Daniel Große, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'05)
Reference:

pp. 4167-4170, Kobe, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formal Verification of LTL Formulas for SystemC Designs




Author:

Daniel Große, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'03)
Reference:

pp. V:245-V:248, Bangkok, 2003
PDF:

[click here]



» Efficient Automatic Visualization of SystemC Designs




Author:

Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst
Conference:
Forum on Specification & Design Languages (FDL'03)
Reference:

pp. 646-657, Frankfurt, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improvements for Constraint Solving in the SystemC Verification Library




Author:

Daniel Große, Rüdiger Ebendt, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 493-496, Stresa, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Estimating Functional Coverage in Bounded Model Checking




Author:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1176-1181, Nice, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking




Author:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 43-48, Philadelphia, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact SAT-based Toffoli Network Synthesis




Author:

Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 96-101, Stresa, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Fast Untestability Proof for SAT-based ATPG




Author:

Daniel Tille, Rolf Drechsler
Conference:
12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Reference:

pp. 38-43, Liberec, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Structural Heuristics for SAT-based ATPG




Author:

Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler
Conference:
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009)
Reference:

pp. 77-82, Florianópolis, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs




Author:

Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler
Conference:
15th IEEE European Test Symposium (ETS)
Reference:

pp. 176-181, Prag, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Task-Driven Software Summarization




Author:

Dave Binkley, Dawn Lawrie, Emily Hill, Janet Burge, Ian Harris, Regina Hebig, Oliver Keszöcze, Karl Reed, John Slankas
Conference:
29th IEEE International Conference on Software Maintenance (ICSM)
Reference:

Eindhoven, The Netherlands, 2013
Hyperlink:

[Link to the Conference]



» Natural Language based Power Domain Partitioning




Author:

David Lemma, Daniel Große, Rolf Drechsler
Conference:
21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 101-106, Budapest, Hungary, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters




Author:

David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Conference:
IEEE Nordic Circuits and Systems Conference (NORCAS)
Reference:

Tallinn, Estonia, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Generation of a Programmable Power Management Unit at the Electronic System Level




Author:

David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Conference:
23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Novi Sad, Serbia, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Minimization of Multi-Valued Decision Diagrams for Incompletely Specified Functions




Author:

Denis Popel and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference:

pp. 241-246, Tokyo, 2003
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Decision Diagrams Optimization Using Copy Properties




Author:

Dragan Jankovic, Radomir Stankovic and Rolf Drechsler
Conference:
Euromicro Symposium on Digital System Design (DSD'2002)
Reference:

pages 236-243, Dortmund, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multi-Valued Logic Functions




Author:

Dragan Jankovic, Radomir Stankovic and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Reference:

pages 76-82, Boston, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Reduction of Sizes of Multiple-Valued Decision Diagrams by Copy Properties




Author:

Dragan Jankovic, Radomir Stankovic, Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004)
Reference:

pp. 229-234, Toronto, 2004
Hyperlink:

[Link to the Conference]



» BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits




Author:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Bengaluru, India, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines




Author:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 129-134, Warschau, Polen, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Strong 8-bit Sboxes with Efficient Masking in Hardware




Author:

Erik Boss, Vincent Grosso, Tim Güneysu, Gregor Leander, Amir Moradi, Tobias Schneider
Conference:
CHES 2016: 171-193
Reference:

http://dx.doi.org/10.1007/978-3-662-53140-2_9



» IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems (Tool Paper)




Author:

Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat
Conference:
International Symposium on Formal Methods (FM)
Reference:

Paris, France, 2012
Hyperlink:

[Link to the Conference]



» Parametric Analysis of Hybrid Systems Using HyMITATOR (Tool Presentation)




Author:

Étienne André, Ulrich Kühne
Conference:
International Conference on Integrated Formal Methods (iFM)
Reference:

Pisa, Italy, 2012
Hyperlink:

[Link to the Conference]



» Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking




Author:

Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 780-785, Dresden, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reliable Integration of Thermal Flow Sensors into Air Data Systems




Author:

Felipe Augusto Braga Viana, Frank Sill Torres
Conference:
7th Brazilian Symposium on Computing System Engineering (SBESC 2018)
Reference:

Salvador, Brazil, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Polynomial Datapath Optimization using Constraint Solving and Formal Modelling




Author:

Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
Conference:
IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Guiding Coverage Metric for Formal Verification




Author:

Finn Haedicke, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC




Author:

Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Symposium on System-on-Chip (SoC)
Reference:

pp. 1-7, Tampere, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Confident Leakage Assessment - A Side-Channel Evaluation Framework based on Confidence Intervals




Author:

Florian Bache, Christina Plump, Tim Güneysu
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, Germany, 2018
Hyperlink:

[Link to the Conference]



» Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models




Author:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
8th International Conference on Tests & Proofs (TAP)
Reference:

pp. 99-116, York, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» From UML/OCL to Base Models: Transformation Concepts for Generic Validation and Verification




Author:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
International Conference on Model Transformation (ICMT)
Reference:

pp. 149-165, L’Aquila, Italy, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards a Catalog of Structural and Behavioral Verification Tasks for UML/OCL Models




Author:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
Modellierung
Reference:

pp. 117-124, Karlsruhe, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level




Author:

Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Reference:

Virtual Conference, Singapore, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Integrated SystemC Debugging Environment




Author:

Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
Conference:
Forum on Specification & Design Languages (FDL)
Reference:

pp. 140-145, Barcelona, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Non-Intrusive High-level SystemC Debugging




Author:

Frank Rogin, Erhard Fehlauer, Steffen Ruelke, Sebastian Ohnewald, Thomas Berndt
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Darmstadt, 2006
Hyperlink:

[Link to the Conference]



» Automatic Debugging of System-on-a-Chip Designs




Author:

Frank Rogin, Rolf Drechsler, Steffen Rülke
Conference:
IEEE International SOC Conference (SOCC)
Reference:

Belfast, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Generation of Complex Properties for Hardware Designs




Author:

Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke
Conference:
Design, Automation, and Test in Europe (DATE)
Reference:

Munich, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» HotAging - Impact of Power Dissipation on Hardware Degradation




Author:

Frank Sill Torres, Alberto Garcia Ortiz and Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

Sapporo, Japan, 2019.
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation




Author:

Frank Sill Torres, Hussam Amrouch, Jörg Henkel and Rolf Drechsler
Conference:
IEEE International Reliability Physics Symposium (IRPS 2019)
Reference:

Monterey, California, USA, March 31 - April 4, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synchronization of Clocked Field-Coupled Circuits




Author:

Frank Sill Torres, Marcel Walter, Robert Wille, Daniel Große, Rolf Drechsler
Conference:
IEEE International Conference on Nanotechnology (Nano)
Reference:

Cork, Ireland, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata




Author:

Frank Sill Torres, Pedro A. Silva, Geraldo Fontes, José Augusto M. Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Prague, Czech Republic, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Unintrusive Aging Analysis based on Offline Learning




Author:

Frank Sill Torres, Pedro F. R. Leite Junior and Rolf Drechsler
Conference:
30th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Reference:

Cambridge, UK, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata




Author:

Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 649-656, Prague, Czech Republic, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Integer Overflow Detection in Hardware Designs at the Specification Level




Author:

Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference:
8th International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
Reference:

Valetta, Malta, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Performance Aspects of Correctness-oriented Synthesis Flows




Author:

Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference:
Int’l Conf. on Model-Driven Engineering and Software Development (MODELSWARD)
Reference:

2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Automatic Hardware Synthesis from Formal Specification to Implementation




Author:

Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Beijing, China, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Lightweight Satisfiability Solvers for Self-Verification




Author:

Fritjof Bornebusch, Robert Wille, Rolf Drechsler
Conference:
7th International Symposium on Embedded Computing and System Design (ISED)
Reference:

Durgapur, Indien, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Ein formaler Ansatz zum Robustheitsnachweis




Author:

Görschwin Fey, Rolf Drechsler
Conference:
Zuverlässigkeit und Entwurf
Reference:

München, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Distributed and Coupled Electrothermal Model of Power Semiconductor Devices




Author:

G. Belkacem, D. Labrousse, S. Lefebvre, P.-Y. Joubert, U. Kühne, L. Fribourg, R. Soulat, E. Florentin, C. Rey
Conference:
International Conference on Renewable Energies and Vehicular Technology
Reference:

Hammamet, 2012
Hyperlink:

[Link to the Conference]



» Designing Reliable Cyber-Physical Systems




Author:

Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Bremen, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Empirical Results on Parity-based Soft Error Detection with Software-based Retry




Author:

Gökçe Aydos, Görschwin Fey
Conference:
IEEE Nordic Circuits and Systems Conference (NORCAS)
Reference:

Oslo, Norway, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploiting Error Detection Latency for Parity-based Soft Error Detection




Author:

Gökçe Aydos, Görschwin Fey
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Košice, Slovakia, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Deterministc Algorithms for ATPG under Leakage Constraints




Author:

Görschwin Fey
Conference:
18th Asian Test Symposium (ATS'09)
Reference:

Taichung, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Orchestrated Multi-level Information Flow Analysis to Understand SoCs




Author:

Görschwin Fey
Conference:
48th Design Automation Conference (DAC)
Reference:

San Diego, USA, 2011
Promotion video on YouTube
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Minimizing the Number of Paths in BDDs




Author:

Görschwin Fey and Rolf Drechsler
Conference:
15th Symposium on Integrated Circuits and System Design
Reference:

pages 359-364, Porto Alegre, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Utilizing BDDs for disjoint SOP minimization




Author:

Görschwin Fey and Rolf Drechsler
Conference:
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Reference:

volume II, pages 306-309, Tulsa, 2002
PS:

[click here]



» Computing Bounds for Fault Tolerance using Formal Techniques




Author:

Görschwin Fey, Andre Sülflow, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 190-195, San Francisco, USA, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formaler Nachweis der Fehlertoleranz von Schaltkreisen




Author:

Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Conference:
GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008)
Reference:

pp. 75-82, Ingolstadt, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the Construction of Small Fully Testable Circuits with Low Depth




Author:

Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools
Reference:

Lübeck, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks




Author:

Görschwin Fey, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1225-1226, Munich, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» BDD Circuit Optimization for Path Delay Fault Testability




Author:

Görschwin Fey, Junhao Shi, Rolf Drechsler
Conference:
Euromicro Symposium on Digital System Design (DSD'2004)
Reference:

pp. 168-172, Rennes, 2004
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Efficiency of Multiple-Valued Encoding in SAT-based ATPG




Author:

Görschwin Fey, Junhao Shi, Rolf Drechsler
Conference:
IEEE International Symposium on Multiple-Valued Logic (ISMVL '06)
Reference:

Singapore, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Basis for Formal Robustness Checking




Author:

Görschwin Fey, Rolf Drechsler
Conference:
International Symposium on Quality of Electronic Design (ISQED)
Reference:

San Jose, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Finding Good Counter-Examples to Aid Design Verification




Author:

Görschwin Fey, Rolf Drechsler
Conference:
First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003)
Reference:

pp. 51-52, Mont Saint-Michel, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Improving Simulation-Based Verification by Means of Formal Methods




Author:

Görschwin Fey, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Reference:

pp. 640-643, Yokohama, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Algorithms for Taylor Expansion Diagrams




Author:

Görschwin Fey, Rolf Drechsler, Maciej Ciesielski
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004)
Reference:

pp. 235-240, Toronto, 2004
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Targeting Leakage Constraints during ATPG




Author:

Görschwin Fey, Sathoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Conference:
Asian Test Symposium (ATS)
Reference:

pp. 225-230, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the Relation Between Simulation-based and SAT-based Diagnosis




Author:

Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1139-1144, Munich, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques




Author:

Görschwin Fey, Sebastian Kinder and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference:

pp. 361-366, Tokyo, 2003
PS:

[click here]



» Reusing Learned Information in SAT-based ATPG




Author:

Görschwin Fey, Tim Warode, Rolf Drechsler
Conference:
20th International Conference on VLSI Design
Reference:

Bangalore, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Graph Transformation Units Guided by a SAT Solver




Author:

Hans-Jörg Kreowski, Susanne Kuske, Robert Wille
Conference:
International Conference on Graph Transformations (ICGT)
Reference:

pp. 27-42, Enschede, 2010
Hyperlink:

[Link to the Conference]



» Automated Optimization of Scan Chain Structure for Test Compression-Based Designs




Author:

Harshad Dhotre, Mehdi Dehbashi, Ulrike Pfannkuchen, Klaus Hofmann
Conference:
IEEE Asian Test Symposium (ATS)
Reference:

Hiroshima, Japan, 2016
Hyperlink:

[Link to the Conference]



» Machine Learning-based Prediction of Test Power




Author:

Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Reference:

Baden Baden, Germany, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Machine Learning Based Test Pattern Analysis for Localizing Critical Power Activity Areas




Author:

Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler
Conference:
30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Reference:

Cambridge, UK, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements




Author:

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Conference:
20th IEEE Latin American Test Symposium (LATS)
Reference:

Santiago, Chile, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Identification of Efficient Clustering Techniques for Test Power Activity on the Layout




Author:

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Conference:
26th IEEE Asian Test Symposium (ATS)
Reference:

Taipei, Taiwan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Constraint-based Pattern Retargeting for Reducing Localized Power Activity during Testing




Author:

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
Conference:
21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Budapest, Hungary, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Diagnosis Using Boolean Satisfiability




Author:

Heinz Riener, Görschwin Fey
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Model-Based Diagnosis versus Error Explanation




Author:

Heinz Riener, Görschwin Fey
Conference:
10th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'12)
Reference:

pp. 43-52, Arlington, Virginia, USA, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» metaSMT: A Unified Interface to SMT-LIB2




Author:

Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL'14)
Reference:

pp. 1-6, Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification




Author:

Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 251-256, Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis




Author:

Heinz Riener, Stefan Frehse, Görschwin Fey
Conference:
Design, Automation and Test in Europe (DATE'13)
Reference:

pp. 939-943, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» KLUZZER: Whitebox Fuzzing on top of LLVM




Author:

Hoang M. Le
Conference:
Automated Technology for Verification and Analysis (ATVA)
Reference:

Taipei, Taiwan, 2019
Hyperlink:

[Link to the Conference]



» LLVM-based Hybrid Fuzzing with LibKluzzer (Competition Contribution)




Author:

Hoang M. Le
Conference:
International Conference on Fundamental Approaches to Software Engineering (FASE)
Reference:

Dublin, Ireland, 2020
Hyperlink:

[Link to the Conference]



» Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing




Author:

Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Florence, Italy, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» From Requirements and Scenarios to ESL Design in SystemC




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

pp. 183-187, Kolkata, WB, India, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Scalable Fault Localization for SystemC TLM Designs




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'13)
Reference:

pp. 35-38, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation




Author:

Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 116:1-6 Austin, Texas, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation




Author:

Hoang M. Le, Rolf Drechsler
Conference:
Design and Verification Conference and Exhibition Europe (DVCon Europe)
Reference:

Munich, Germany, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC




Author:

Hoang M. Le, Rolf Drechsler
Conference:
Design and Verification Conference and Exhibition Europe (DVCon Europe)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Verifying Determinism of SystemC Designs




Author:

Hoang M. Le, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'14)
Reference:

pp. 153:1-4, Dresden, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study




Author:

Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1160-1163, Dresden, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Resiliency Evaluation via Symbolic Fault Injection on Intermediate Code




Author:

Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 845-850, Dresden, Germany, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improved Fault Diagnosis for Reversible Circuits




Author:

Hongyan Zhang, Robert Wille, Rolf Drechsler
Conference:
Asian Test Symposium (ATS)
Reference:

New Delhi, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability




Author:

Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
10th IEEE Africon
Reference:

Livingstone, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Nano Security: From Nano-Electronics to Secure Systems




Author:

Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer
Conference:
Design, Automation and Test in Europe Conference (DATE)
Reference:

Grenoble, France, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» IND-CCA Secure Hybrid Encryption from QC-MDPC Niederreiter




Author:

Ingo von Maurich, Lukas Heberle, Tim Güneysu
Conference:
Post-Quantum Cryptography (PQCrypto 2016)
Reference:

pages 1-17, LNCS Vol. 9606, Fukuoka, Japan
Hyperlink:

[Link to the Conference]



» Standard lattices in hardware




Author:

James Howe, Ciara Moore, Máire O'Neill, Francesco Regazzoni, Tim Güneysu, K. Beeden
Conference:
Design Automation Conference (DAC), Austin, USA, 2016, 162:1-162:6
Reference:

http://doi.acm.org/10.1145/2903150.2907756



» Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns




Author:

Jan Malburg Alexander Finder Görschwin Fey
Conference:
7. ITG/GMM/GI-Fachtagung Zuverlässigkeit und Entwurf (ZuE2013)
Reference:

pp. 59-66, Dresden, Germany, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques




Author:

Jan Malburg Niklas Krafczyk Görschwin Fey
Conference:
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 21-26, Warschau, Polen, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Feature Localization for Hardware Designs using Coverage Metrics




Author:

Jan Malburg, Alexander Finder, Görschwin Fey
Conference:
Design Automation Conference (DAC)
Reference:

pp. 941-946, San Francisco, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Tuning Dynamic Data Flow Analysis to Support Design Understanding




Author:

Jan Malburg, Alexander Finder, Görschwin Fey
Conference:
Design, Automation and Test in Europe (DATE'13)
Reference:

pp. 1179-1184, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Property mining using dynamic dependency graphs




Author:

Jan Malburg, Tino Flenker, Goerschwin Fey
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Verification For Train Control Systems




Author:

Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004)
Reference:

pp. 252-265, Braunschweig, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State-of-the-Art and Research Challenges




Author:

Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Gruettner, Thomas Kruse, Christoph Kuznik, Hoang M. Le, Andreas Mauderer, Wolfgang Mueller, Daniel Mueller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, Simon Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Conference:
Design Automation Conference (DAC)
Reference:

pp. 113:1-6, San Francisco, 2014
Hyperlink:

[Link to the Conference]



» Building Fast Multi-Agent Systems using Hardware Design Languages for High-Throughput Systems




Author:

Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler
Conference:
6th International Conference on Dynamics in Logistics (LDIC)
Reference:

Bremen, Germany, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips




Author:

Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Bochum, Germany, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Feature Localization for Dynamically Generated SystemC Designs




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'15)
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Cone of Influence Analysis at the Electronic System Level Using Machine Learning




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Santander, Spain, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Natal, Brazil, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Validating SystemC Implementations Against Their Formal Specifications




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic




Author:

Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 465-470, Rhode Island, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Enhancing Fundamental Energy Limits of Field-Coupled Nanocomputing Circuits




Author:

Jeferson Figueiredo Chave, Marco Ribeiro, Frank Sill Torres, Omar Paranaiba Vilela Neto
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

Florence, Italy, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» High-Performance and Lightweight Lattice-Based Public-Key Encryption




Author:

Johannes A. Buchmann, Florian Göpfert, Tim Güneysu, Tobias Oder, Thomas Pöppelmann
Conference:
IoTPTS@AsiaCCS 2016: 2-9
Reference:

http://doi.acm.org/10.1145/2899007.2899011



» Towards a Model-Based Verification Methodology for Complex Swarm Systems




Author:

Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[Link to the Conference]



» Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models




Author:

Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Generic Representation of CCSL Time Constraints for UML/MARTE Models




Author:

Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL




Author:

Judith Peters, Robert Wille, Rolf Drechsler
Conference:
International Conference on Engineering of Complex Computer Systems (ICECCS)
Reference:

pp. 116-125, Tianjin, China, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Determining Relevant Model Elements for the Verification of UML/OCL Specifications




Author:

Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1189-1192, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Refinement Checking for Formal System Models




Author:

Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler
Conference:
Twelfth Asian Test Symposium (ATS03)
Reference:

p.290-293, Xi'an, 2003
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Bridging Fault Testability of BDD Circuits




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005)
Reference:

pp. 188-191 Shanghai, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» PASSAT: Efficient SAT-based Test Pattern Generation




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Conference:
IEEE Annual Symposium on VLSI (ISVLSI '05)
Reference:

pp.212-217, Tampa, Florida, 2005
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
Conference:
International Conference on ASIC (ASICON 2005)
Reference:

pp. 967-970, Shanghai, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SPIHT implemented in a XC4000 device




Author:

Jörg Ritter, Görschwin Fey and Paul Molitor
Conference:
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Reference:

volume I, pages 239-242, Tulsa, 2002
PDF:

[click here]



» Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture




Author:

Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler
Conference:
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Virtual Conference, Dallas, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploiting Negative Control Lines in the Optimization of Reversible Circuits




Author:

Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 209-220, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation




Author:

Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler
Conference:
IEEE Design and Test Symposium 2012 (IDT)
Reference:

Doha, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles




Author:

Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Gran Canaria, Spain, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters




Author:

Kemal Çağlar Coşkun, Muhammad Hassan, Rolf Drechsler
Conference:
25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Prague, Czech Republic, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-IPs




Author:

Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs




Author:

Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler
Conference:
International Symposium on Applied Reconfigurable Computing (ARC)
Reference:

Darmstadt, Germany, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Dynamic Execution Environment for System Security Protection against Hardware Flaws




Author:

Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 557-562, Hong Kong SAR, China, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips




Author:

Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor




Author:

Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
Conference:
IEEE Design, Automation and Test in Europe
Reference:

Vol. I, pp. 162-167, Paris, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debugging of Reversible Circuits using πDDs




Author:

Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 316-321, Toyama, Japan, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation




Author:

Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library




Author:

Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Kolkata, India, 2016
Hyperlink:

[Link to the Conference]



» Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking




Author:

Luca Amaru, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Design criteria of a thermal mass flow sensor for aircraft air data applications




Author:

Lucas C. Ribeiro, Rubens A. Souza, Michael Lopes Oliveira, S.P.L. Vieira, W.O. Avelino, Clarice F.R. Oliveira, Davies Wiliiam de Lima Monteiro, Frank Sill Torres, Roana M.O. Hansen
Conference:
31st Congress of the International Council of the Aeronautical Sciences (ICAS 2018)
Reference:

Belo Horizonte, Brazil, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding




Author:

Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große
Conference:
IEEE International Symposium on Circuits & Systems (ISCAS)
Reference:

Daegu, Korea, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL




Author:

Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler
Conference:
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Reference:

Oslo, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Secure architectures of future emerging cryptography SAFEcrypto




Author:

Máire O'Neill, Elizabeth O'Sullivan, Gavin McWilliams, Markku-Juhani Saarinen, Ciara Moore, Ayesha Khalid, James Howe, Rafaël Del Pino, Michel Abdalla, Francesco Regazzoni, Felipe Valencia, Tim Güneysu, Tobias Oder, Adrian Waller, Glyn Jones, Anthony Barnett, Robert Griffin, Andrew Byrne, Bassem Ammar, David Lund
Conference:
Conf. Computing Frontiers 2016: 315-322
Reference:

http://doi.acm.org/10.1145/2903150.2907756



» Analyzing Dependability Measures at the Electronic System Level




Author:

Marc Michael, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 1-8, Oldenburg, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Localizing Features of ESL Models for Design Understanding




Author:

Marc Michael, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Vienna, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks




Author:

Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference:
34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Reference:

Athens, Greece, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection




Author:

Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference:
40th IEEE VLSI Test Symposium (VTS)
Reference:

San Diego, USA, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods




Author:

Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Reference:

Barcelona, Spain, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verification for Field-coupled Nanocomputing Circuits




Author:

Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, USA, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Exact Method for Design Exploration of Quantum-dot Cellular Automata




Author:

Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 503-508, Dresden, Germany, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Scalable Design for Field-coupled Nanocomputing Circuits




Author:

Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Tokyo, Japan, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Bail on Balancing: An Alternative Approach to the Physical Design of Field-coupled Nanocomputing Circuits




Author:

Marcel Walter, Robert Wille, Frank Sill Torres, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Limassol, Cyprus, 2020
Best Paper Candidate
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Design Automation for Field-coupled Nanotechnologies




Author:

Marcel Walter, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Limassol, Cyprus, 2020
Best Student Forum Paper Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» One-pass Synthesis for Field-coupled Nanocomputing Technologies




Author:

Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Tokyo, Japan, 2021
Best Paper Candidate
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» The System Verification Methodology for Advanced TLM Verification




Author:

Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
Conference:
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Reference:

pp. 313-322, Tampere, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fast Heuristics for the Edge Coloring of Large Graphs




Author:

Mario Hilgemeier, Nicole Drechsler and Rolf Drechsler
Conference:
Euromicro Symposium on Digital System Design (DSD'2003)
Reference:

pp. 230-237, Antalya, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Minimizing the Number of One-Paths in BDDs by an Evolutionary Algorithm




Author:

Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
Conference:
Congress on Evolutionary Computation 2003 (CEC2003)
Reference:

Vol.3, pp.1724-1731, Canberra, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Depth Optimized Synthesis of Symmetric Boolean Functions




Author:

Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Tampa, Florida, USA, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Polynomial Formal Verification of Approximate Adders




Author:

Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Gran Canaria, Spain, 2022
Hyperlink:

[Link to the Conference]



» Polynomial Formal Verification of Approximate Functions




Author:

Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Pafos, Cyprus, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Better Late Than Never: Verification of Embedded Systems After Deployment




Author:

Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Florence, Italy, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fredkin-Enabled Transformation-based Reversible Logic Synthesis




Author:

Mathias Soeken, Anupam Chattopadhyay
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reverse Engineering with Simulation Graphs




Author:

Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
Conference:
Formal Methods in Computer Aided Design (FMCAD)
Reference:

Austin, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automating the Translation of Assertions Using Natural Language Processing Techniques




Author:

Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris and Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» BDD Minimization for Approximate Computing




Author:

Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 474-479, Macao, China, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Coverage of OCL Operation Specifications and Invariants




Author:

Mathias Soeken, Julia Seiter, Rolf Drechsler
Conference:
9th International Conference on Tests & Proofs (TAP)
Reference:

L’Aquila, Italy, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» White Dots do Matter: Rewriting Reversible Logic Circuits




Author:

Mathias Soeken, Michael Kirkedal Thomsen
Conference:
Reversible Computation
Reference:

pp. 196-208, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Quality Assessment for Requirements based on Natural Language Processing




Author:

Mathias Soeken, Nabila Abdessaied, Arman Allahyari-Abhari, Andi Buzo, Liana Musat, Georg Pelz, Rolf Drechsler
Conference:
Special Session at the Forum on Specification & Design Languages (FDL'14)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Enumeration of reversible functions and its application to circuit complexity




Author:

Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli
Conference:
Reversible Computation
Reference:

Bologna, Italy, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Optimizing Majority-Inverter Graphs With Functional Hashing




Author:

Mathias Soeken, Pierre-Emmanuel Gaillardon, Luca Amaru, Giovanni De Micheli
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Synthesis Flow for Sequential Reversible Circuits




Author:

Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 299-304, Victoria, Canada, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesis of Reversible Circuits with Minimal Lines for Large Functions




Author:

Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 85-92, Sydney, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Window Optimization of Reversible and Quantum Circuits




Author:

Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 431-435, Vienna, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying UML/OCL Models Using Boolean Satisfiability




Author:

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1341-1344, Dresden, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Eliminating Invariants in UML/OCL Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1142-1145, Dresden, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Assisted Behavior Driven Development Using Natural Language Processing




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
50th International Conference on Objects, Models, Components, Patterns (TOOLS)
Reference:

pp. 269-287, Prague, Czech Republic, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
5th International Conference on Tests & Proofs (TAP)
Reference:

pp. 152-170, Zurich, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying Dynamic Aspects of UML Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1077-1082, Grenoble, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Grammar-based Program Generation Based on Model Finding




Author:

Mathias Soeken, Rolf Drechsler
Conference:
IEEE Design and Test Symposium 2013 (IDT)
Reference:

Marrakesch, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An MIG-based Compiler for Programmable Logic-in-Memory Architectures




Author:

Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
Conference:
Design Automation Conference (DAC)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Property Generation for the Formal Verification of Bus Bridges




Author:

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Conference:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 417-422, Cottbus, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits




Author:

Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 173-178, Victoria, Canada, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Self-practicing of logic circuits through mobile devices: Lecturers' and students' perceptions




Author:

Mazyar Seraj, Cornelia Große, Rolf Drechsler
Conference:
The 9th annual International Conference on Education and New Learning Technologies (EduLearn17)
Reference:

Barcelona, Spain, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Look What I Can Do: Acquisition of Programming Skills in the Context of Living Labs




Author:

Mazyar Seraj, Cornelia Große, Serge Autexier, Rolf Drechsler
Conference:
The IEEE/ACM 41st International Conference on Software Engineering: Software Engineering Education and Training (ICSE-SEET)
Reference:

Montréal, QC, Canada, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Smart Homes Programming: Development and Evaluation of an Educational Programming Application for Young Learners




Author:

Mazyar Seraj, Cornelia Große, Serge Autexier, Rolf Drechsler
Conference:
The 18th ACM International Conference on Interaction Design and Children (IDC)
Reference:

Boise, Idaho, USA, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Scratch and Google Blockly: How Girls’ Programming Skills and Attitudes are Influenced




Author:

Mazyar Seraj, Eva-Sophie Katterfeldt, Kerstin Bub, Serge Autexier, Rolf Drechsler
Conference:
The 19th Koli Calling International Conference on Computing Education Research (Koli Calling)
Reference:

Koli, Finland, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Impacts of Creating Smart Everyday Objects on Young Female Students' Programming Skills and Attitudes




Author:

Mazyar Seraj, Eva-Sophie Katterfeldt, Serge Autexier, Rolf Drechsler
Conference:
The 51st ACM Technical Symposium on Computer Science Education (SIGCSE)
Reference:

Portland, Oregon, USA, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Impacts of Block-based Programming on Young Learners' Programming Skills and Attitudes in the Context of Smart Environments




Author:

Mazyar Seraj, Rolf Drechsler
Conference:
The 25th ACM annual conference on Innovation and Technology in Computer Science Education (ITiCSE)
Reference:

Trondheim, Norway, 2020
Hyperlink:

[Link to the Conference]



» BEESM, a Block-Based Educational Programming Tool for End Users




Author:

Mazyar Seraj, Serge Autexier, Jan Janssen
Conference:
The 10th Nordic Conference on Human-Computer Interaction (NordiCHI)
Reference:

Oslo, Norway, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Dynamic Template Matching with Mixed-polarity Toffoli Gates




Author:

Md Mazder Rahman, Mathias Soeken, Gerhard W. Dueck
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits




Author:

Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Design Debugging in a Testbench-Based Verification Environment




Author:

Mehdi Dehbashi, André Sülflow, Görschwin Fey
Conference:
14th Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 479-486, Oulu, Finland, 2011
Best Paper Candidate
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Formal Verification of X Propagation with Respect to Testability Issues




Author:

Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß
Conference:
IEEE International Design and Test Symposium 2014 (IDT)
Reference:

pp. 106-111, Algiers, Algerien, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Application of Timing Variation Modeling to Speedpath Diagnosis




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
4th International Conference on System, Software, SoC and Silicon Debug (S4D)
Reference:

pp. 34-37, Vienna, Austria, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Debugging from Pre-Silicon to Post-Silicon




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 324-329, Tallinn, Estonia, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Post-Silicon Debugging of Design Bugs




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
3rd International Conference on System, Software, SoC and Silicon Debug (S4D)
Reference:

pp. 67-71, Munich, Germany, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Post-Silicon Debugging of Failing Speedpaths




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
21st IEEE Asian Test Symposium (ATS)
Reference:

pp. 13-18, Niigata, Japan, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debug Automation for Synchronization Bugs at RTL




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
27th International Conference on VLSI Design
Reference:

pp. 44-49, Mumbai, India, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Automated Speedpath Debugging




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 48-53, Karlovy Vary, Czech Republic, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SAT-Based Speedpath Debugging Using Waveforms




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
19th IEEE European Test Symposium (ETS)
Reference:

Paderborn, Germany, 2014
Hyperlink:

[Link to the Conference]



» Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
22nd Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP)
Reference:

Turin, Italy, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Functional Analysis of Circuits Under Timing Variations




Author:

Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Conference:
17th IEEE European Test Symposium (ETS)
Reference:

pp. 177, Annecy, France, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On Modeling and Evaluation of Logic Circuits Under Timing Variations




Author:

Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Conference:
15th Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 431-436, Izmir, Turkey, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fault Effects in FlexRay-Based Networks with Hybrid Topology




Author:

Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi
Conference:
3rd IEEE International Conference on Availability, Reliability and Security (ARES)
Reference:

pp. 491-496, Barcelona, Spain, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Scalable Simulation-based Verification of SystemC-based Virtual Prototypes




Author:

Mehran Goli, Rolf Drechsler
Conference:
EUROMICRO Digital System Design Conference (DSD)
Reference:

Kallithea - Chalkidiki, Greece, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique




Author:

Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Conference:
38th IEEE International Conference on Computer Design (ICCD)
Reference:

Hartford, USA, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Debugging-Aware Visualization Technique for SystemC HLS Designs




Author:

Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Palermo, Sicily, Italy, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» AIBA: an Automated Intra-Cycle Behavioral Analysis for SystemC-based Design Exploration




Author:

Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
IEEE International Conference on Computer Design (ICCD)
Reference:

Phoenix, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Equivalence Checking for SystemC-TLM 2.0 Models Against their Formal Specifications




Author:

Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata




Author:

Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
35th IEEE International Conference on Computer Design (ICCD)
Reference:

Boston Area, Massachusetts, USA, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques




Author:

Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
IEEE International Symposium on Rapid System Prototyping (RSP), 2018
Reference:

Torino, Italy, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Analysis of Virtual Prototypes at Electronic System Level




Author:

Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Conference:
29th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

Washington, D.C., USA, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs




Author:

Mehran Goli, Rolf Drechsler
Conference:
26th Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Tokyo, Japan, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Design Understanding of SystemC-based Virtual Prototypes: Data Extraction, Analysis and Visualization




Author:

Mehran Goli, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Limassol, Cyprus, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs




Author:

Mehran Goli, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Munich, Germany, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes




Author:

Mehran Goli, Rolf Drechsler
Conference:
Forum on Specification & Design Languages (FDL)
Reference:

Antibes, France, 2021
Best Paper Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Behaviour Driven Development for Tests and Verification




Author:

Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference:
8th International Conference on Tests & Proofs (TAP)
Reference:

pp. 61-77, York, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and its Permutation Semantics




Author:

Michael Kirkedal Thomsen, Mathias Soeken, Robin Kaarsgaard
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Cell Library Design for Ultra-Low Power Internet-of-Things Applications




Author:

Michael Lopes Oliveira, Keyliane Fernandes, Frank Sill Torres
Conference:
3rd International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT 2018)
Reference:

Bento Gonçalves, Brazil, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Augmented Sifting for Multiple-Valued Decision Diagrams




Author:

Michael Miller and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference:

pp. 375-382, Tokyo, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the Construction of Multi-Valued Decision Diagrams




Author:

Michael Miller and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Reference:

pages 245-253, Boston, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Switching Activity Estimation for Finite State Machines for Low Power Synthesis (Poster)




Author:

Mikael Kerttu, Per Lindgren, Mitch Thornton and Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'02)
Reference:

Scottsdale, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions




Author:

Milan Funck, Vladimir Herdt, Rolf Drechsler
Conference:
25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Prague, Czech Republic, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Multi-Output Timed Shannon Circuits




Author:

Mitch Thorton, Rolf Drechsler and Michael Miller
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002)
Reference:

pages 47-52, Pittsburgh, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Debugging Sequential Circuits Using Boolean Satisfiability




Author:

Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith
Conference:
IEEE International Conference on Computer Aided Design (ICCAD'04)
Reference:

pp. 204-209, San Jose, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Post-Verification Debugging of Hierarchical Designs




Author:

Moayad Ali, Sean Safarpour, Andreas Veneris, Magdy Abadir, Rolf Drechsler
Conference:
IEEE International Conference on Computer Aided Design (ICCAD'05)
Reference:

pp. 871-876, San Jose, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Multi-Objective Synthesis of Quantum Circuits Using Genetic Programming




Author:

Moein Sarvaghad-Moghaddam, Philipp Niemann, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 220-227, Leicester, UK, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» TLM Protocol Compliance Checking at the Electronic System Level




Author:

Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Conference:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 435-440, Cottbus, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Polynomial Word-Level Verification of Arithmetic Circuits




Author:

Mohammed Barhoush, Alireza Mahzoon, Rolf Drechsler
Conference:
International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

Beijing, China, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Data Flow Testing for SystemC-AMS Timed Data Flow Models




Author:

Muhammad Hassan, Daniel Große, Hoang M. Le, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Florence, Italy, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Testbench Qualification for SystemC-AMS Timed Data Flow Models




Author:

Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 857-860, Dresden, Germany, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» System Level verification of Phase-Locked Loop using Metamorphic Relations




Author:

Muhammad Hassan, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe Conference (DATE)
Reference:

Grenoble, France, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations




Author:

Muhammad Hassan, Daniel Große, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Tokyo, Japan, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Functional Coverage-Driven Characterization of RF Amplifiers




Author:

Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich and Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Southampton, United Kingdom, 2019
Best Paper Candidate
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Early SoC Security Validation by VP-based Static Information Flow Analysis




Author:

Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

pp. 400-407, Irvine, USA, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Data Flow Testing for Virtual Prototypes




Author:

Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Adaptive Branch and Bound using SAT to Estimate False Crosstalk




Author:

Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
Conference:
International Symposium on Quality of Electronic Design (ISQED)
Reference:

San Jose, 2008
Hyperlink:

[Link to the Conference]



» Timing Arc Based Logic Analysis for False Noise Reduction




Author:

Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
Conference:
IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Reference:

pp. 225-230, San Jose, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reversible Circuit Rewriting with Simulated Annealing




Author:

Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, and Rolf Drechsler
Conference:
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Reference:

Daejeon, Korea, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Template Matching Using Boolean Satisfiability




Author:

Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 328-333, Toyama, Japan, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Quantum Circuit Optimization by Hadamard Gate Reduction




Author:

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Technology mapping for quantum circuits using Boolean functional decomposition




Author:

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Technology mapping of reversible circuits to Clifford+T quantum circuits




Author:

Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler
Conference:
46rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reducing the Depth of Quantum Circuits Using Additional Lines




Author:

Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 221-233, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Self-Adaptive Evolutionary Many-Objective Optimization based on Relation Epsilon-Preferred




Author:

Nicole Drechsler
Conference:
International Conference on Soft Computing MENDEL
Reference:

Brno, Czech Republic, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred




Author:

Nicole Drechsler, André Sülflow, Rolf Drechsler
Conference:
International Conference on Evolutionary Computation Theory and Applications (ECTA)
Reference:

Vilamoura, Portugal, 2013
Hyperlink:

[Link to the Conference]



» Exploration of Sequential Depth by Evolutionary Algorithms




Author:

Nicole Drechsler, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (VLSI'03)
Reference:

pp. 81-85, Darmstadt, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Conservatively Analyzing Transient Faults




Author:

Niels Thole, Görschwin Fey, Alberto Garcia-Ortiz
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Montpelier, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking on ESL Utilizing A Priori Knowledge




Author:

Niels Thole, Heinz Riener, Görschwin Fey
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Bremen, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking on System Level using A Priori Knowledge




Author:

Niels Thole, Heinz Riener, Görschwin Fey
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Reference:

Belgrade, Serbia, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Hybrid Algorithm to Conservatively Check the Robustness of Circuits




Author:

Niels Thole, Lorena Anghel, Görschwin Fey
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Pittsburgh, USA, 2016
Hyperlink:

[Link to the Conference]



» A Hybrid Algorithm to Conservatively Check the Robustness of Circuits




Author:

Niels Thole, Lorena Anghel, Görschwin Fey
Conference:
IEEE European Test Symposium (ETS)
Reference:

Amsterdam, Niederlande, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Early Verification of ISA Extension Specifications Using Deep Reinforcement Learning




Author:

Niklas Bruns, Daniel Große, Rolf Drechsler
Conference:
30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

Beijing, China, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing




Author:

Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

Irvine, CA, USA, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging




Author:

Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
Conference:
Design, Automation and Test in Europe Conference (DATE)
Reference:

Antwerp, Belgium, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» WCET Overapproximation for Software in the Context of Cyber-Physical Systems




Author:

Niklas Krafczyk, Heinz Riener, Görschwin Fey
Conference:
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Reference:

Tallinn, Estonia, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Checking Concurrent Behavior in UML/OCL Models




Author:

Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler
Conference:
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

Ottawa, Kanada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fault Detection in Parity Preserving Reversible Circuits




Author:

Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verification-driven Design Across Abstraction Levels - A Case Study




Author:

Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Frame Conditions in Symbolic Representations of UML/OCL Models




Author:

Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

pp. 65-70, Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models




Author:

Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler
Conference:
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

pp. 77-86, Vienna, Austria, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Contradiction Analysis for Inconsistent Formal Models




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Reference:

Belgrade, Serbia, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

Saint Malo, Brittany, France, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Leveraging the Analysis for Invariant Independence in Formal System Models




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» (Semi-)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications




Author:

Oliver Keszöcze, Betina Keiner, Matthias Richter, Gottfried Antpöhler, Robert Wille
Conference:
Special Session at the Forum on specification & Design Languages (FDL'14)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSID)
Reference:

Pune, Indien, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A General and Exact Routing Methodology for Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Routing for Digital Microfluidic Biochips with Temporary Blockages




Author:

Oliver Keszöcze, Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact One-pass Synthesis of Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On overcoming photodetector saturation due to background illumination while maintaining high sensitivity by means of a tailored CMOS pixel




Author:

Pablo Nunes Agra Belmonte, Lucas Chaves, Frank Sill Torres, Davies William de Lima Monteiro
Conference:
Global LiFi Congress
Reference:

Paris, France, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level




Author:

Pascal Pieper, Ralf Wimmer, Gerhard Angst, Rolf Drechsler
Conference:
31st ACM Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

Virtual Conference, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes




Author:

Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, USA, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools




Author:

Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, USA, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype




Author:

Pascal Pieper, Vladimir Herdt, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

Irvine, CA, USA, 2022
Hyperlink:

[Link to the Conference]



» Hiding Higher-Order Side-Channel Leakage - Randomizing Cryptographic Implementations in Reconfigurable Hardware




Author:

Pascal Sasdrich, Amir Moradi, Tim Güneysu
Conference:
RSA Conference Cryptographers’ Track (CT-RSA)
Reference:

San Francisco, US, 2017.
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» White-Box Cryptography in the Gray Box - A Hardware Implementation and its Side Channels




Author:

Pascal Sasdrich, Amir Moradi, Tim Güneysu
Conference:
FSE 2016: 185-203
Reference:

http://dx.doi.org/10.1007/978-3-662-52993-5_10



» A grain in the silicon: SCA-protected AES in less than 30 slices




Author:

Pascal Sasdrich, Tim Güneysu
Conference:
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2016: 25-32
Reference:

http://dx.doi.org/10.1109/ASAP.2016.7760769



» Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability




Author:

Payam Habiby, Sebastian Huhn, Rolf Drechsler
Conference:
28th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Reference:

Apulia, Italy, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains




Author:

Payam Habiby, Sebastian Huhn, Rolf Drechsler
Conference:
33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Reference:

Frascati (Rome), Italy, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formal Verification on Register Transfer Level - Utilizing High-Level Information for Hardware Verification




Author:

Peer Johannsen and Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (VLSI'01)
Reference:

pages 127-132, Montpellier, 2001
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers




Author:

Philipp Niemann, Alexandre A. A. de Almeida, Gerhard Dueck, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Portorož, Slowenien, 2020
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Construction of QMDDs for Irreversible, Reversible and Quantum Functions




Author:

Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 214-231, Kolkata, India, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» T-Depth Optimization for Fault-Tolerant Quantum Circuits




Author:

Philipp Niemann, Anshu Gupta, Rolf Drechsler
Conference:
49th IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Fredericton, NB, Canada, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures




Author:

Philipp Niemann, Chandan Bandyopadhyay, Rolf Drechsler
Conference:
Design, Automation and Test in Europe Conference (DATE)
Reference:

Grenoble, France, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Assisted Generation of Frame Conditions for Formal Models




Author:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Conference:
Design, Automation and Test in Europe (DATE'15)
Reference:

pp. 309-312, Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Extracting Frame Conditions from Operation Contracts




Author:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Conference:
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

pp. 266-275, Ottawa, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation




Author:

Philipp Niemann, Luca Müller, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Palermo, Sicily, Italy, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Finding Optimal Implementations of Non-native CNOT Gates using SAT




Author:

Philipp Niemann, Luca Müller, Rolf Drechsler
Conference:
Reversible Computation (RC)
Reference:

Nagoya, Japan, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Analyzing Frame Conditions in UML/OCL Models: Consistency, Equivalence, and Independence




Author:

Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
6th International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
Reference:

pp. 139-151, Funchal, Portugal, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Logic Synthesis for Quantum State Generation




Author:

Philipp Niemann, Rhitam Datta, Robert Wille
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 247-252, Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 483-488, Singapore, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking in Multi-level Quantum Systems




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 201-215, Kyoto, Japan, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improved Synthesis of Clifford+T Quantum Functionality




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 597-600, Dresden, Germany, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 125-140, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic




Author:

Philipp Niemann, Rolf Drechsler
Conference:
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Dallas, USA, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic




Author:

Philipp Niemann, Rolf Drechsler
Conference:
51st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Nursultan, Kazakhstan, 2021
Hyperlink:

[Link to the Conference]
Recording:

[Link to the Recording]
PDF:

[click here]



» Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions




Author:

Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille
Conference:
Reversible Computation
Reference:

pp. 248-264, Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» RTL-Datapath Verification using Integer Linear Programming




Author:

Raik Brinkmann and Rolf Drechsler
Conference:
IEEE VLSI Design'02 & Asia and South Pacific Design Automation Conference
Reference:

pages 741-746, Bangalore, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Property-driven Timestamps Encoding for Timeprints-based Tracing and Monitoring




Author:

Rehab Massoud, Hoang M. Le, Rolf Drechsler
Conference:
17th International Conference on Formal Modeling and Analysis of Timed Systems, (FORMATS)
Reference:

Amsterdam, Netherlands, 27-29 August, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Temporal Tracing of On-Chip Signals using Timeprints




Author:

Rehab Massoud, Hoang M. Le, Peter Chini, Prakash Saivasan, Roland Meyer and Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

Las Vegas, USA, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction




Author:

Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
Conference:
15th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS)
Reference:

pp. 335-351, Berlin, Germany, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reliability Analysis Reloaded: How Will We Survive?




Author:

Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda
Conference:
Design, Automation and Test in Europe (DATE'13)
Reference:

Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling




Author:

Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto Garcia-Ortiz, Rolf Drechsler
Conference:
24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)
Reference:

Costa Brava, Spain, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Introduction to Reversible Circuit Design




Author:

Robert Wille
Conference:
Saudi International Electronics, Communications and Photonics Conference (SIECPC)
Reference:

Riyadh, 2011
Hyperlink:

[Link to the Conference]



» Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits




Author:

Robert Wille, Aaron Lye, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 489-494, Singapore, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification




Author:

Robert Wille, André Sülflow, Rolf Drechsler
Conference:
International Conference on Modeling, Simulation and Visualization Methods (MSV)
Reference:

pp. 36-39, Las Vegas, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Design of Microfluidic Devices: An Overview of Platforms and Corresponding Design Tasks




Author:

Robert Wille, Bing Li, Rolf Drechsler and Ulf Schlichtmann
Conference:
In Forum on specification & Design Languages (FDL), München, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fast Exact Toffoli Network Synthesis of Reversible Logic




Author:

Robert Wille, Daniel Große
Conference:
IEEE International Conference on Computer Aided Design (ICCAD)
Reference:

pp. 60-64, San Jose, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking of Reversible Circuits




Author:

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Conference:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 324-330, Naha, Okinawa, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SMT-based Stimuli Generation in the SystemC Verification Library




Author:

Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 1-6, Sophia Antipolis, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reversible Logic Synthesis with Output Permutation




Author:

Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Conference:
22nd International Conference on VLSI Design
Reference:

pp. 189-194, New Delhi, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» RevLib: An Online Resource for Reversible Functions and Reversible Circuits




Author:

Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability




Author:

Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 411-416, Montpellier, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debugging of Toffoli Networks




Author:

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1284-1289, Nice, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SWORD: A SAT like Prover Using Word Level Information




Author:

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Reference:

pp. 88-93, Atlanta, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking




Author:

Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 542-549, Parma, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Quantified Synthesis of Reversible Logic




Author:

Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große
Conference:
Design, Automation, and Test in Europe (DATE)
Reference:

pp. 1015-1020, Munich, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization




Author:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 120-125, Chennai, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits




Author:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 29-34, Toyama, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» RevVis: Visualization of Structures and Properties in Reversible Circuits




Author:

Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-coupled Nanotechnologies




Author:

Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Miami, Florida, USA, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards a Generic Verification Methodology for System Models




Author:

Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1193-1196, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines




Author:

Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 145-150. Yokohama, Japan, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Designing a RISC CPU in Reversible Logic




Author:

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 170-175, Tuusula, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic




Author:

Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 213-218, Amherst, USA, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines




Author:

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 69-74, Victoria, Canada, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debugging of Inconsistent UML/OCL Models




Author:

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1078-1083, Dresden, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reducing the Number of Lines in Reversible Circuits




Author:

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 647-652, Anaheim, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Compact and Efficient SAT Encoding for Quantum Circuits




Author:

Robert Wille, Nils Przigoda, Rolf Drechsler
Conference:
IEEE Africon
Reference:

Mauritius, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reverse BDD-based Synthesis for Splitter-free Optical Circuits




Author:

Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits




Author:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[Link to the Conference]



» Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs




Author:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Bologna, Italy, 2016
Hyperlink:

[Link to the Conference]



» Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits




Author:

Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Macao, China, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Determining the Minimal Number of Lines for Large Reversible Circuits




Author:

Robert Wille, Oliver Keszöcze, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1204—1207, Grenoble, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesis of Approximate Coders for On-chip Interconnects Using Reversible Logic




Author:

Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto Garcia-Ortiz
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formal Methods for Emerging Technologies




Author:

Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2015
Hyperlink:

[Link to the Conference]



» BDD-based Synthesis of Reversible Logic for Large Functions




Author:

Robert Wille, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 270-275, San Francisco, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» The SyReC Hardware Description Language: Enabling Scalable Synthesis of Reversible Circuits




Author:

Robert Wille, Rolf Drechsler
Conference:
International Midwest Symposium on Circuits and Systems (MWSCAS)
Reference:

Columbus, USA, 2013
Hyperlink:

[Link to the Conference]



» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis




Author:

Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SyReC: A Programming Language for Synthesis of Reversible Circuits




Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 184-189, Southampton, 2010
Received Best Paper Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploiting Reversibility in the Complete Simulation of Reversible Circuits




Author:

Robert Wille, Simon Stelter, Rolf Drechsler
Conference:
IEEE Africon
Reference:

Mauritius, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» FoREnSiC - An Automatic Debugging Environment for C Programs




Author:

Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
Conference:
Haifa Verification Conference (HVC)
Reference:

Haifa, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
IEEE Design and Test Symposium 2012 (IDT)
Reference:

Doha, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluation of Static Variable Ordering Heuristics for MDD Construction




Author:

Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Reference:

pages 254-260, Boston, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» JADE: Implementation and Visualization of a BDD Package in JAVA




Author:

Rolf Drechsler
Conference:
IEEE Design, Automation and Test in Europe (DATE'02) - User Forum
Reference:

page 259, Paris, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» PolyAdd: Polynomial Formal Verification of Adder Circuits




Author:

Rolf Drechsler
Conference:
24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Vienna, Austria, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesizing Checkers for On-line Verification of System-on-Chip Designs




Author:

Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'03)
Reference:

pp. IV:748-IV:751, Bangkok, 2003
PDF:

[click here]



» Reachability Analysis for Formal Verification of SystemC




Author:

Rolf Drechsler and Daniel Große
Conference:
Euromicro Symposium on Digital System Design (DSD'2002)
Reference:

pages 337-340, Dortmund, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fast and Efficient Equivalence Checking based on NAND-BDDs




Author:

Rolf Drechsler and Mitch Thornton
Conference:
IFIP International Conference on Very Large Scale Integration (VLSI'01)
Reference:

pages 401-405, Montpellier, 2001
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms




Author:

Rolf Drechsler and Nicole Drechsler
Conference:
21st IASTED International Multi-Conference Applied Informatics (AI 2003)
Reference:

Innsbruck, 2003
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Polynomial Formal Verification of Arithmetic Circuits




Author:

Rolf Drechsler, Alireza Mahzoon, Lennart Weingarten
Conference:
International Conference on Computational Intelligence and Data Engineering (ICCIDE)
Reference:

Vijayawada, India, 2021
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Polynomial Formal Verification of Complex Arithmetic Circuits




Author:

Rolf Drechsler, Alireza Mahzoon, Mehran Goli
Conference:
25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Prague, Czech Republic, 2022
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?




Author:

Rolf Drechsler, Andreas Breiter
Conference:
2nd International Conference on Software and Data Technologies
Reference:

Barcelona, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hardware Project Management – What we Can Learn from the Software Development Process for Hardware Design?




Author:

Rolf Drechsler, Andreas Breiter
Conference:
4th Conference of Informatics and Information Technologies
Reference:

Bitola, 2003
Hyperlink:

[Link to the Conference]



» Code is Ethics —Formal Techniques for a Better World




Author:

Rolf Drechsler, Christoph Lüth
Conference:
EUROMICRO Digital System Design Conference (DSD)
Reference:

Kallithea - Chalkidiki, Greece, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Future SoC Verification Methodology: UVM Evolution or Revolution?




Author:

Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev
Conference:
Design, Automation and Test in Europe (DATE'14)
Reference:

Dresden, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems




Author:

Rolf Drechsler, Daniel Große
Conference:
Asian Test Symposium (ATS)
Reference:

Kolkata, India, 2019
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying Next Generation Electronic Systems




Author:

Rolf Drechsler, Daniel Große
Conference:
International Conference on Infocom Technologies and Unmanned Systems (ICTUS)
Reference:

pp. 6 - 10, Dubai, United Arab Emirates, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synchronized Debugging across Different Abstraction Levels in System Design




Author:

Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow
Conference:
embedded world Conference 2013
Reference:

Nürnberg, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Integrated Approach for Combining BDD and SAT Provers




Author:

Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Conference:
International Conference on VLSI Design
Reference:

Hyderabad, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Self-Verification as the Key Technology for Next Generation Electronic Systems




Author:

Rolf Drechsler, Hoang M. Le, Mathias Soeken
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hardware/Software Co-Visualization on the Electronic System Level using SystemC




Author:

Rolf Drechsler, Jannis Stoppe
Conference:
International Conference on VLSI Design
Reference:

Kolkata, India, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits




Author:

Rolf Drechsler, Junhao Shi and Görschwin Fey
Conference:
IEEE Great Lakes Symposium on VLSI (GLSV'03)
Reference:

p. 80-83, Washington, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Envisioning Self-Verification of Electronic Systems




Author:

Rolf Drechsler, Martin Fränzle, Robert Wille
Conference:
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Reference:

Bremen, Germany, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hardware-Software Co-Visualization: Developing Systems in the Holodeck




Author:

Rolf Drechsler, Mathias Soeken
Conference:
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 1-4, Karlovy Vary, Czech Republic, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 53-58, Vienna, Austria, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated and Quality-driven Requirements Engineering




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille,
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Completeness-Driven Development




Author:

Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Conference:
International Conference on Graph Transformation
Reference:

pp. 38-50, Bremen, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits




Author:

Rolf Drechsler, Robert Wille
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 78-85, Tuusula, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]